Yes, I worked a bit on P. Monta’s hi res photo and made some progress regarding the HP 35.
This is a rather low study to guess and sketch by hand (well by eye … and mouse) the different layers (diffusion, gate, contact …) …
Peter Monta crafted tools to extract the layers from the background picture but it is mainly operator wise.
And it is sometimes difficult to resolve ambiguity between contacts and gates (at least for me! ) and the ‘context’ is a big help.
But nevertheless, this 1971 process is rather simple. It’s silicon gates + metal + diffusion layer.
Connectivity is of metal and diffusion and they appear on the hi res pic.
The metal strips appear in ‘yellow’ and the diffusion connexions are visible as thin lines.?
All in all, I found it hard to do the bottom-up work alone.?A top-down approach has been in many cases (so far) helpful.
As always - in reverse engineering - it’s easier to find something when you know what you search.
- the PMOSFET close to the ground line are ‘pull up’ pmos (with depletion loads),
- the transistors connected at Vgg follow precharging capacitors and the gate clocked by phi1 and will be followed by the gate clocked by phi2,
- the global signal distribution map on the chip helps a lot when working on a small portion.
Another help is symmetry.
The routing of the tracks seems have been drawn by hand (not by a computer).
And man likes symmetry. This assumption helps a lot
See for example, top of the pic, the 8 flip flops are a SIPO (Serial In Parallel Out) shifter and at the bottom the 10 flip flops are a PISO ( Parallel In Serial Out ) register.
Below a remarkable 3 flip flop pattern.
The first group is the ROM address register, the second is the instruction register and below the 3 latches are the word select WS register (facing bit 2, 3, 4 of Is register)
Another example of symmetry is found in the routing of the address and instruction register ; the lines follows the same order but mirrored : phi2, phi1, Vss, set, reset, Gnd, Vgg.
Now my results so far (I don’t know about Peter, he’s probably ahead … I will check with him) :
I will give a full report on the ROM page of the site (as soon as I’m sure of myself!).
1) I have deciphered the way the rom matrix is addressed : row and column selection.
That’s an explanation of the 8 latch address register, 3 latch column selection and 5 latch row selection (top left of the image).
Electronically, the 8 bit register address consists of a two phase latch circuit (with an inverter for the Q bar output).
I understand clearly how the ROM matrix feeds the PISO register.
2) I understand ‘globally’ how the instruction register works, how the WS register is addressed and where it is located (bottom part of the picture).?
The instruction register is also a two phase latch circuit.
I hope all this will be of interest to you.
If you are particularly interested in something, just tell me.
ps: RIP Steve Jobs ; we'll miss you ....