HP-35 chip images and schematics

Hi Peter,
Very impressive work. First class! Congratulations!
This time we can see the circuit. I can't believe it!

Yes but what a work. A mountain of work!

For the ROM, the interest is rather low IMHO, since it is just a shifter, pushing the bits serially on the Is bus.
Maybe more light on how the ROM output enable flip flop is working, would be interesting.
But this part of the machine is well understood, now.

But for the A&R ..... what a treat.
How the instruction decoder works would be instructive, though the state of the art, at the start of the 70's is well documented (4004).
How the RPN stack is implemented and how the display data is decoded.....

Note the C&T too -at the PMOS FET level- would be of great interest (the Wilkes control unit - the machine in the machine!)....

IHO, the reverse engineering of such a complex logic from the P MOSFET array would be a very huge project.

Nice challenge for the youngest!

Thank you for sharing,
Cheers!

ps: For each of the photos, Have you identified the links to the outside pins?
I would be helpful to guess the functional zones.

Beautiful,
On the left side, we can see the 8 bit address internal bus and on the right the 10 bit instruction internal bus (externally the ROM bus is serial).

The lower part (what you called 'logic') is probably the 'rom select decoder' and the 'rom output enable flip flop'.
Note the instruction register (10 bits) is clearly (on the left) connected to Is : the bits are shifted on Is, gated by the clock phi2.

Cheers!

Hi Peter,
Working on your photo (hi res version) of the HP-35's A&R, the top right pattern puzzled me!
Now I got it.

Photo P.Monta 2010

It is -very probably- the machine register structure.
Left to Right the 7 registers :  first the 3 main registers  A, B, C (52 bits) (the 4 missing bits connected to the display decoder must be somewhere else - probably top left)  and next  the rest of the stack - 4 registers : D, E, F, M (56 bits each, the height is bigger).
My two cents!

Should be easier with the pin naming

A&R pin naming and internal connections (11/21/2010)

Cheers!
Jacques.

Erratum : Nov 27, 2012
P. Monta's image (AMI 1820-0848) and the A&R I have decapped (MOSTEK 1820-1169) don't match.
My apologies.
The pinout names consequently are inverted upside down.
Vss is bottom right
D0 is top left.
See below B. Rosa's post.

ps to my erratum

The A&R decapped (MOSTEK 1820-1169) is the same that the one encapsulated in the HP65 Hybrid Circuit.

I comment the full-resolution image of the HP-35's ROM that P.Monta posted recently.

The link above on the HP-Museum doesn't seem to work anymore.

Here is a permanent link : HP_35 ROM Macro HI RES (17MB)

Now a few points regarding the ROM PMOS cell array.

We can easily see the P MOSFET junctions (bit ‘1’) or their absence (‘0’) because the pattern was determined early in the fabrication process by MOSTEK or AMI according to HP’s specifications (diffusion of p-type and n-type dopants).
It is a rather ancient process (1970) and costly comparing to “mask programming” in which the MOSFETs are fabricated at all bit locations.
Ultimately during a step called metallization a layer of aluminum is coating the surface of the wafer, leaving metal only where intersections (rows, columns) are required.   

On the center of the P.Monta's photo, we can see the 32 rows linked to the row decoder and the 80 (8 * 10) columns connected to sense amplifiers and Vdd (on the structure of a MOSFET ROM see Sedra/Smith “Microelectronic CIRCUITS” (5 ed.) p.1048.)

The row close the column sense (8 bit bus) & decoder is the 31rst.

I have drawn the marks of each cell (MOSFET or nothing) on a sheet of paper and deciphered the first two instructions of this 31rst line :

(took Peter's photo upside down to have the 8 bit bus line top position)

Row 0 contains all bits [9 ..0] of instructions number 0 to 7
Row 1 contains all bits [9 ..0] of instructions number 8 to 15
….   
Row 31 contains all bits [9 ..0] of instructions number 248 to 255    
Row j contains all bits [9 ..0] of instructions number  j*8 to (j*8)+7

On this 31rst row

Instruction 0    

b9  b8  b7  b6  b5   b4   b3    b2    b1   b0
0    0    0    0    0    1     1     1     1     0    

is @ address 248 or 370 octal if in ROM 0 (just the photographer can tell!).

But it could be 1370 octal if in ROM 1 or 2370 octal if in ROM 2.

Comparing to the listing, it’s address 1370 octal symbolic instruction ‘if b[s]=0’

Next, Instruction 1 is
0    0    0    0    0     0     0     1     1     1
address 1371 octal ‘goto 00’

Cheers,
Jacques.

Very interesting thread.
I was wondering if there is news since november 2010.
It would be of great interest to learn more about this famous chip.

Thank you anyway
dave.

Hello Peter & Jacques,

What a great site and what a great achievement the HP-35 was! 

I’ve been studying the A&R chip photo for several weeks now.

I, too, would like to understand its workings in greater detail, hopefully ending up with a full logic diagram and schematic, just as Jacques has done so nicely for the PCB.  Why stop the investigation of this wonderful machine at the boundaries of the LSI?  Let’s go all the way!

I started by determining the pinouts (those shown in Jacques’ previous posts are incorrect, I believe).  Note that input Is is actually the complement of Is (as described in the HP-45 patent).  It and Ia are inverted between the chips to save power.

Then I then identified the structure and schematic for the bits making up the storage registers.  There are six pmos transistors per bit.

Then I did the same for the D-type flip flops, of which A(4), B(4), C(4), and the instruction registers are composed, and some of the other major logic blocks.  I’ll share these details in future posts if there is any interest.

I’ve included an annotated image of the A&R with the major subsections highlighted.  The areas that aren’t yet highlighted have proved more difficult to figure out “by hand”.  For example, I haven’t been able to locate the 4 bit counter used by the display decoder, nor the carry flip flop, or the display toggle flip flop, nor the decimal point flip flop.

There’s something very interesting going on with the serial adder, which I don’t fully understand yet.  Dave Cochran spends very little time in his patent applications on the serial adder, stating that its operation is “well known in the art”, and providing a couple of references which I’ve read.

From what I can tell so far, the adder on the A&R chip does not do the“add-6” function in the conventionally described manner, with 2 full adders (one for the intermediate sum, one to add six if necessary) interconnected with a 4 bit holding register.

It appears that part of the BCD correction (add-6) logic is actually incorporated in the A(4), and C(4) registers, and more of the correction logic is a part of the 4 bit holding register.  WTF????

If anyone has any insight on how this adder actually implements the add-6 correction, I’d love to hear about it.

Since I’m not sure it’s going to be possible for me to fully decode all of this chip’s functionality with a strictly manual approach (find the transistors, draw the schematics, find the gates, decode the logic, etc.), I’d also be interested in getting more details about Peter’s approach using his home-brew tools.  I feel like I need some tools to deal with the complexity, and I’d rather not build my own if someone has already done so.

Hi Bob,

Here is a beginning of an explanation, from Dave Cochran himself:
« For the first three clock times, the addition is strictly binary. At the fourth clock time the binary sum is checked, and if the answer is more than 1001 (nine), then the sum is corrected to decimal by adding 0110 (six). »
http://www.hpmemory.org/wb_pages/d_cochran_01.htm

Thank You Bob for your carefully annotated image :-)
Francois.

Hi Jacques,

Thanks for your reply.  I'm making good, but very slow, progress in mapping out the A&R chip.  I'm about finished with the part of the circuit which receives and decodes the instructions from the Is (and Sync) input pins and latches them in the instruction buffer.  I'll post these details when they are completed. 

One interesting and unexpected discovery so far is that the 2 bit counter which counts the 4 bit times within a digit time does not count in straight binary.  It counts in Grey code (00, 01, 11, 10).

Also, it appears that the multiple word-time shifting as described in Cochran's patent 3781820 (W1, W2, W3, W4) with an "advance" tap for the second operand to the adder is *not* done in the HP-35 A&R! 

Each individual 56 bit register (A thru F, and M) has its own independent input gating / selector circuit, controlled by signals from the instruction decoder. 

So all the shifting between registers called for by an instruction during word time t is completed in the following word time (t + 1) - much simpler.

The 2 adder inputs also have their own input selector circuitry, which is tied to the outputs from the A, B, and C "racetrack" registers at their "bit zero" positions.  No "advance taps" required or present in the actual chip implementation.

It's also interesting to think about the fact that the WS signal associated with a given instruction must be delayed by one word time from when its associated instruction is sent to A&R. 

This will need to be kept in mind when I (hopefully) begin decoding the C&T chip's internals.

In looking closely at the HP-65 chip photo you posted, it appears clear that its A&R chip is laid out somewhat differently than the hi-res photo of the HP-35 A&R Peter Monta has shared (which I am using for my investigations).   In fact, the one you posted with pinouts originally looks different than Peter's A&R. 

I'm pretty sure what I posted is correct for Monta's version of the A&R.

How do I embed a photo or drawing in a post on this forum?  This will make my future posts and explanations (hopefully) a lot clearer than just attaching stuff at the end of the post.

Thanks for your help!

Bob Rosa

Hi Jacques,

I'm making good progress in mapping the details of the A&R chip.   I now have a complete logic gate and flip flop diagram of this chip, and am in the process of error checking it and simulating its operation. 

In reading US Patent 4001569, (ROM description, column 7, lines 42-56) Cochran states that a design decision was made "to invert all outputs to save power."  He then goes on to state that the signals on the Is and Ia lines (specifically) are inverted.  Which is it?  All signals or just Is & Ia?

My question relates to the SYNC and WS signal inputs to the A&R chip.  Since SYNC (especially) is at logic zero (consuming power in the output drivers) for the majority of time during the word cycle, it would make sense for it (and WS) to *also* be inverted to save power.

I do not have an HP-35 to conclusively determine the polarity of these signals for myself.  Would you be so kind as to do so for me? 

I know you put some photos of the sync signal on your website (which indicate non-inverted operation), but they answer the question only if I assume that the scope input is DC coupled, and that its "invert" control has not been operated.

Specifically, is the SYNC signal at logic 0 (+6 volts) or logic 1(GND) when active during bit times 45 to 54?  Based upon my logic diagram the SYNC signal *must* be inverted.  If it is not, then I have made an error which I will need to locate.  I don't want to make an incorrect assumption when a direct observation can be taken (with your help).

Thanks in advance for any help you can provide regarding this question.

P.S. - a couple of other interesting discoveries:

1.  The D(56) and F(56) registers are actually reversed from what is shown in my original annotated jpeg of the chip.

2.  I can now see in detail how the "add-6" correction to BCD add/subtract is implemented *without incurring a 4 bit delay* as is typical of the correction algorithm in textbook descriptions and of the patented circuits I've studied.  It's quite ingenious.  I can post details if there is interest, after I complete verification of the chip.

Hi Jacques,

Thanks for your prompt reply!

Your video answered my question perfectly, although we may interpret it differently.

Since pmos logic is negative logic (logic 0 = +6 volts, logic 1 = 0 volts) (or logic 0 = 0 volts, logic 1 = -6 volts), the SYNC signal between the chips at the board level *is* in fact inverted as your photo shows (SYNC pulse active during b45 to b54 is +6 volts or logic 0).

It is inverted back to negative logic (SYNC pulse active during b45-b54 = GND, or logic 1) after being received at input pin 4.  The input circuit following pin 4 inside the chip is actually a D type flip flop whose output feeds an inverter before being fed into the rest of the decoder logic.

Can you observe WS to see if it exhibits this same behavior (active WS signal between chips is the more positive voltage)?

Thanks for your help and I hope to have the logic diagram and description ready to be presented and shared soon.

Bob