HP-35 Arithmetic & Register chip.

The Arithmetic and register (A&R) circuit shown below provides specialized arithmetic functions. It is a P-MOS circuit that requires 2 levels of voltages Vss (6v) and Vgg (-12v).

 Photo D. Weed 2007

 Besides the two phase clock, there are 3 input lines:

 -         Is 10 bit instructions from Roms,
 -         WS the “word select” signal to perform operations on a part of the machine word only, from Roms,
 -         SYNC the synchronization pulse, from C&T,

and seven output lines:

-         the carry line that signals to the C&T that a “carry” occurs in an operation in the adder,
-         the reset signal or START to the cathode driver to reset the LED scanning,
-         and 5 lines to the anodes transistors that multiplex the display data.

The registers of the A&R are 56 bit serial register implemented using MOS technology that is to say that the data (logic 0 or 1) is represented by a charge on a internal capacitance and must be continually refreshed so each register continually re circu­lates on the data path.

The unit contains seven (7) dynamic registers A-F a storage register M and a serial BCD adder - subtractor  (each register consists of 14 * 4 bits cells (56 bits): 10 digit of mantissa, a 2 digit exponent and signs for the mantissa and exponent.

The seven registers are:

-         the working registers A, B, and C with C also being the bottom register of a four-register stack;
-         the next 4 registers C, D, E, and F form the operational stack;
-         and a separate storage register M communicating with the other registers through register C.

The user knows some of the 7 registers by the names of X (display), Y, Z and T (top of the stack) namely registers C, D, E, and F

 - A, B are general purpose registers, C is the display: (A, B, and C can all be interchanged),

- Register P is a 4 bit "pointer" used for field addressing (offset into the working registers),

- the Status register holds the 12 bits of programmable status (S0-S11).

Register C always holds a normalized version of the displayed data.

Either register A or C is connected to one adder input, and either register B or C to the other.

The adder output can be directed to either register A or C.

Certain instructions can generate a carry via the carry flip-flop which is used by the C&T to determine conditional branching.

In the serial decimal adder a correction (addition of 6) to a BCD sum must be made if the sum is greater than 9  (a similar correction for subtraction is necessary) :

Binary, BCD 9 = 1001
Binary 0xA = 1010, 0xB = 1011, 0xC = 1100, 0xD = 1101, 0xE = 1110, 0xF = 1111 (does not exist in BCD)

Hex 0xA + 0x6 = hex 10 (means 10 in BCD) : digit "1" (4 bits "0001") and digit "0" (4 bits "0000").

This is accomplished by adding a four-bit holding regis­ter and inserting the corrected sum into a portion of register A if a carry is generated (box A(4)).

The A&R receives the instruction during bit time b45- b54.

There are 2 types of instructions decoded by the circuit:

- Arithmetic & Register instructions (type 2),
- Data entry and Display instructions (type 5).

Type 2 instructions have a binary  « 10 » in the least significant two bits of its binary pattern.

The “opcode” portion is coding the kind of arithmetic instruction (see fig 3) and the WS 3 bit field codes the portion of the register concerned by the instruction (fig 4).

Each instruction is 10 bit long.

The least significant two bits are “10”:

The 3 bit field SSS is used to select part of the register (WS =  Word Select)

The 5 last bits YYYYY are used to select an arithmetic instruction (256 instructions = 32 * 8 are available)

For example, adding A and C and putting the result in C is coded “01110” (octal 16).

If the instruction is required to operate on the mantissa the WS part is “001”

And the whole 10 bit instruction opcode is

“0111000110”

Fig 3 Type 2 “arithmetic instructions”

When the combination « 10 » is detected, the most significant five bits are saved and decoded by instruction decoder.

The A&R instructions are enabled only when the Word Select signal (WS=logic 1) generated in one of the ROM or in C&T circuit, when WS at logic 0, recirculation of all registers continues.

Word Select field

The « Data entry » and « Display » instructions are also decoded by A&R since the circuit partially decodes display.

Fig 4 « Data entry » and « Display » instructions (X means don't care)

Are concerned: 
- up stack,
- down stack,
- rotate down,
- memory exchange M<->C,
- load constant in C at pointer P position the latter will be decremented,
- recall memory,
- clear registers
- display on,
- display toggle.

In the A&R, the display decoder partially decodes the BCD digits into seven segments (a-g) and a decimal point (dp).

As there is only five output lines (A-E) the display signal is multiplexed during the bit time T1, T2, T3, T4, of each digit time:

-         output line D carries the segment e informa­tion during T1 (the first bit time of each digit time) and the segment d information during T2 (the second bit time of each digit time);

-         output line E carries the seg­ment g information during T I , the segment f informa­tion during T2, and the decimal point (dp) during T4

-         output line C carries the seg­ment c information during T I & T2,

-         etc (see the chronogram fig 5).

The A register is setup to hold the displayed number with the digits in the proper order.

The B regis­ter is used as a masking register with digits 9 inserted for each display position that is to be blanked and a digit 2 at the decimal point location.

The decimal point is not allocated a register position; but it has a full digit position in the output display : one digit and the decimal point share one of the 14 digit times.

When the anode driver of output display unit detects a decimal point code during T4, it provides a signal to the cathode driver of the output display unit to move to the next digit position.

The digit 9 mask in register B allows both trailing and leading zeros to be blanked (i.e., by programming 9's into the B register).

Use of all three working registers for display (the C register to retain the number in normalized form, the A register to hold the number in the displayed form, and the B register as a mask) allows the calculator to have easily both a floating point and a scientific display format. This scheme will be used in all Classic & Woodstock calculators.

Figure 5 represents the ALU's data paths.

Instruction types in the A&R are represented by an arrow linking to registers ; numbers above each arrow is related to the right description text box.

Only Instructions types 2 and 5 are decoded by the A&R ; we give here a description of the rest of the instruction set (instruction examples taken in the HP-35 version 2 ROM):

Type 1 – decoded by the C&T and all A&R registers simply re circulate:

jump subroutine (256 addressed)

 

conditional branch (256 addressed)

 

Type 2 A&R (with possibly WS)

Type 3 – decoded by the C&T:

status operations (37 used)

Type 4- in the C&T used by A&R:

pointer operations (30 used)

Type 5 Data I/O


 

Type 6- decoded by ROM

Rom select

 
subroutine return

 

Type 7 to 9: reserved

Type 10: NOP

 Figure 6 represents the chronogram of the multiplexed display signal.

 Figure 7 represents the bit pattern of instruction types.

 

J. Laporte
April 2008, revisited Nov 2010 (Thanks to Pietro for his help).