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Has anyone here attepmpted to design (and build) a modern MLDL/EPROM box? It should be possible to do it using just programmable logic and a prom.
In fact, since all the development can be done using one the PC emulators, an OTP prom should suffice.
Any ideas? Anyone interested in working on this?
Cheers,
/ji
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I restarted on the HP41 about a year ago. I'm using it mainly toghether with the HP3421A data logger. Since then I could even get hold of a 64KB Eramco Rambox. What a great item! I was also thinking of building another rambox using modern development methods. I'm sure that there is still quite a large interest in ramboxes. I should have a closer look at the various schematics for ramboxes. The address decoding could possibly be done by using a GAL or even PIC microcontroller. Yes I'm interested to take part in such a project and will think about it a bit closer during the next weeks.
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Yes, I had thought of a PIC as a controller.
It's an interesting concept.
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Though I have experience with the PICs I thought about using a XILINX CPLD for such a task. The PIC could serve as an I/O controller from the PC to the device.
The PIC might be possible, but includes not enough memory for building a single chip device. If I'd need more chips, I'd do it in hardware, which would possibly even draw less power, considering the low clock frequencies of the 41.
I own the XILINX Foundation development system (I also built and sold industrial PIC programmers), but I'd think it would be better using an open solution like the XILINX webpack. Building such a chip should be a matter of some days.
I thought about that for months, but had a project with top priority. When I get this finished (next week), I could try to take one of the schematics around and put it into a XILINX.
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It's good to see that there is still interest in hacking the venerable HP41!
I set out yesterday to just build the MLDL described in PPC Journal V9N3, and to my horror I realized that some of the 40xx series chips are no longer available (at least, not from DigiKey, Arrow, or JDR). And we thought that vacuum tubes were hard to get!
All the logic should be doable in an FPGA (or even a CPLD), and for memory we can just use a serial EEPROM with the SPI bus, for example, an ATMEL 25256. There are some things to be careful about, though:
1. Bits on the HP41 ISA and DATA buses are sent out LSB-first, whereas the serial EEPROMs expect them MSB-first.
This means that when we program the EEPROMs, we have to be careful to reverse the order of bits. Also, since the serial eeproms autoincrement the address and keep pumping out data bits so long as they are getting a clock, we can simply use two eeprom words for a ten-bit HP41 instruction and throw out the remaining six bits of the second address.
2. We should just program the thing from a serial port on a PC; no need to actually use the HP41's bus. This frees up a lot of logic that would have to be used to decode the DATA line, and to interpret the 040 (WRITE S&X) instruction that the MLDL used to write to its RAM.
3. Using surface-mounted devices, the logic and the
eeprom chips can easily fit inside an old module. Right now, I'm collecting as many modules as I can find cheap!
4. When the time comes to design the logic, let's form a mailing list to discuss it (or we can just discuss it here). I can host the list and the archives.
I'll post some more ideas I've had about this later.
/ji
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Does it really matter that the chip expects the data MSB first and the HP41 sends it LSB first?
if this happens in both directions, then all that happens is that the data is reversed in the EEPROM.
Back to what was being discussed on a previous message... The serial nature of the IO seems to me to make this ideal for a PIC. It could have a clock that is asynchronous with the HP41 (as the HP41 is somewhat slow. The PIC could manage the serial memory, and interface to the HP41, reversing bits (if you desire) and handling the addressing.
How many write cycles do you get on those serial EEPROMS these days?
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You're right with the PIC, but the problem is, that the PIC solution would be a completely new development, whereas the CPLD solution would be a new implementation of some solution, that has already worked.
I believe, that it should be 10000 to 100000 cycles minimum depending on the device. Real world conditions should show abt 10 times that value. In one of my PIC projects, I reprogrammed a 16C84 more than 1000 times (the program memory), while this device is (was) rated abt 100 times.
I really like the PIC processors and work with them professionally, but it's a matter of development time and that is costly.
I have to finish a project til Thursday and will have zilch time til then, but I'm ready to part in development of such a device (maybe both implementations ?). A new MLDL should fit into a single module port and not in a card reader like case like in the old days.
I could also imagine a general I/O interface (memory mapped) - another reason for XILINX, because of the Pin count.
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One issue to be careful with is that the clocking changes between reading the ISA bus for addresses (the bits change with the rising edge of Phi2, and are ready for reading by the time Phi1 goes up), whereas we should output the instruction bits within a few nanoseconds of Phi2 going up. I'll have to check with my logic analyzer again on Tuesday, but there may not be enough time to execute even one PIC instruction between the time Phi2 goes high and the time a typical ROM module responds. I think the actual requirements may not be as stringent (I believe the bits on ISA are read by the CPU on the rising edge of Phi1), but we would have to experiment with that.
About CPLDs: it's been a long time since I've done any real design; are there any free or reasonably priced development tools out there?
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I'd use the free XILINX webpack, but you'd need the programming cable...
PIC programmers are easier to build...
Does anybody have a substitute for the plug in the 41C modules ???
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As much as I hate to suggest it, the easiest solution is probably to rip the guts out of a commonly (and cheaply available module (memory module) and connect a ribbon cable to it (for development).
Implimentation could use the same approach.
That is, unless anyone who did module doubling has a stock of empty modules.
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The preferred way to connect an MLDL to a 41 was the printer cable, which HP was selling as a spare part after 1982 and for several years. I guess one can also cannibalize an HPIL cable (I just got one on ebay for $20).
On of the commercially available eprom boxes was inside a card reader case.
Ideally, I would like to get everything to fit inside a single module (which should not be hard; a PIC or CPLD and a serial EEPROM), with a tiny connector on the back that could be used to (re)program the thing by talking directly to the EEPROM.
While we are at it, can someone recommend a cheap (or free) PCB-design program that will generate output suitable to send to a PCB manufacturing place such as www.pcbexpress.com?
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English freeware for Win/Linux available at:
http://www.cadsoftusa.com/
or better:
http://www.cadsoft.de/cgi-bin/download.pl?page=/home/cadsoft/html_public/download.htm.de&dir=pub/program/4.0
German Version at www.cadsoft.de
While the site seems to be in German language, the Software is available in German and English. There's also a tutorial in both languages..
I just try it out now and it seems to be nice.
There are three limits for the freeware
The PCB size of max 100*80mm (4 x 3.2 ")
There's only two signal and two power layers.
There's only one schematic page possible.
Not too bad considering, that the software's free.
There's a lot of free development software on the net.
Yes, you're right, everything should (and can) fit into a single module.
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Forgive the ignorance of one who hasn't yet acquired a HP41, but what is the purpose of this Rambox? Is it for switching between eproms, or expanding memory, or is it an eprom-emulator in RAM space, or what?
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You can use an HP-41 RAM box as a module simulator.
From the useer's point of view, it's organized as a multiple of 4K (times 10 bit) blocks.
Usually you have functions to copy other 4K blocks from and to the RAM box, and to develop your own machine language programs (e.g. David Assembler).
Of course you could even use a RAM box as a data container.
Raymond
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Oh please!!!! do!!! I used to run a configuration with the
32K version of the Eramco Ram and I loved it!! I have been trying for close to 5 years to find a simulator which would
provide this full capability.. If a rom could be programed with the 8K eramco operating system, you would have a friend for life.
Tom...
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You probably missed my posting -- I have a PIC-based ROM emulator working. It can hold five 4K ROM images, and it even supports banking. The parts cost $20 at DigiKey. I don't have power management running yet, so it always draws 50mA when it's on -- not the sort of thing you want to carry with you. Right now it's just a breadboard thing (I'm finishing the wire-wrap version over the weekend), but ideally it should be done with SMT components so it fits inside a module cover.
I'm probably not going to bother with full MLDL functionality (so, no writes from the HP41). V41 is much better suited to debugging and developing, and once a rom is sufficiently debugged, it can be transferred onto the PIC.
Look in http://www.tla.org/hp41/ for pretty pictures. I'll post more stuff there soon.
/ji
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I am also interested in this project...
Small runs of new module cases could be manufactured
the cost might not even be prohibitive, I will ask around.
Regardless if you start building these let me know,
you have at least one ready client.
PS please don't canibalize the last HPIL...I still need one.
Miguel
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It's not only the case, it's the plug, that should be found and (re)designed.
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I have thought of building one of these using the Scenix microprocessor chip. It is PIC compatible, runs at up to 100 million instructions per second, has a 4K erasable memory, and is available in a teenie tiny package that could fit in a canabalized memory module package. It could probably be done as a single chip solution for programs a little under 4K bytes (larger chips may be available by now). Although the chip would draw quite a bit of current at full bore (around 1mA/MHz), it has a power down mode that draws about zero power.
I have forgotten where the 41 bus, etc is documented though and have not attempted to research it further. Does anyone know where to look for the proper documentation?
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> I have forgotten where the 41 bus, etc is documented
> though and have not attempted to research it further.
> Does anyone know where to look for the proper
> documentation?
PPC Journal Volume 7 Number 3, and the HP41 service manual.
Spending some time with a logic analyzer also helps get a
better feel for the relative timings.
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Both of these sources are available on my HP-41 archive website: www.hp41.org
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I just fear, that the high clock frequencies of processors will rise the current consumption of the system. A single chip solution is attracting, so this might be an argument for doing it this way.
Unfortunately my "real" job wont let me do such projects in these days - maybe in one or two weeks.
I'd be ready to contribute in PIC and in CPLD development lines.
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I am currently in the process (just started) of building an FPGA based MLDL. I have just finished with the VHDL code for the phase counter, and intend to post everything on my website, but that will take about a month or so.
I have not decided on any hardware yet, but I am using the Cypress version of Warp.
Meindert
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