Anyone know what became of the NEWT project?



#6

Hi all. I am wondering if the NEWT (souped up very fast 41 coconut compatible custom processor) ever got built?

I wonder if it is worth reviving?

Anyone with documents (other than the 134 page PDF document I have)
could write to me as I may have a crack at it if it can be done.

Rather long term project though...

Thanks,

Don Wallace
donwallace63@yahoo.com.au


#7

There is some more information at http://www.systemyde.com/hp41


I am about halfway through the process of verifying the instruction set. I haven't looked at the turbo operation yet. The design fits in the target FPGA.


All of the voltage translation circuitry is designed, but I have a couple more things to do in the power supply, and I need to add an external latch to detect the "memory clear" state because the MMU information is held in RAM and won't be valid when starting from battery insertion.


I haven't started the board design yet because I need to learn Eagle first.


Monte Dalrymple


#8

If any help is needed: my MLDL2000 is done in Eagle, and I know it quite well now. I gladly offer my support (after I have gone through the entire MLDL2000 production of course).
What is the target FPGA by the way?

Meindert


#9

Thanks for the Eagle offer. I need to learn it for other projects too, though. But if I get stuck I may ask a question or two.


I am using an Actel Pro-ASIC-Plus, specifically the APA075 in a 144 pin TQFP package, to hold the design.

Monte Dalrymple


#10

Aside from not needing a separate configuration memory, was your choice influenced by any other notable advantages of the Actel parts over those of other vendors (e.g., Xilinx, Altera)?


#11

The Actel parts are flash-based and are live at power-up. This allows me to exactly replicate the power-up behavior of the original design. SRAM-based FPGAs have huge power-on current requirements. You're probably thinking "configure it once and leave it powered, with the clock turned off". Unfortunately, the SRAM parts that are large enough to hold the design have quiescent current requirements of 1-5mA. This is going to eat batteries quickly. With the flash-based parts I will actually power-down the FPGA and include discrete logic to do the power-on detect. Of course, the design is technology-independent, so if someone wants to implement it in another technology that will certainly be possible (intellectual property issues aside).

Monte


#12

Thanks everyone for the replies. Interesting...

Hope it all goes together well, Monte...

Don W


#13

Hi all.

Hi Monte.

I just checked out your compnany website.

WOW!

Don W

#14

Quote:
SRAM-based FPGAs have huge power-on current requirements.

The recent ones (e.g., Xilinx Spartan 3) don't.

Quote:
With the flash-based parts I will actually power-down the FPGA and include discrete logic to do the power-on detect.

Makes sense. The Panasonic/Quasar HHC (Hand Held Computer) from 1981 did that. It used an NMOS 6502, because there wasn't yet a CMOS part.
It ran a Forth-like language called "SNAP", but I've never found the technical documentation on it.

I imagine that you're already taking care to make sure that the I/O pins of the FPGA are also open or grounded when power is removed. Otherwise, any inputs that are driven high by external circuitry (buffers, etc.) will cause substantial leakage current as the ESD protection clamp diodes effectively power the chip from the I/O pins.


#15

Yes, I have to create a virtual "pad ring" to translate between
the 3.3V FPGA signals and the 6V Nut-compatible signals. During
power-down all FPGA inputs are clamped Low and all FPGA outputs
have high-impedance pull-downs to provide a DC path to ground
outside the FPGA itself.

I also have to be careful during operation to keep all FPGA inputs within the 3.3V FPGA supply rail.

The "pad ring" is why I have to learn the schematic entry/pcb
layout tools, because it's a small pile of SMT devices. If the
board only needed the FPGA and memories I could just do a hand-
layout board.


#16

This looks like it will really work. I have done the same with the MLDL2000. I switch off the 3.3V power regulator when the NUT CPU is not running to save battery.
I would strongly recommend against hand layout. Eagle is free for non-commercial (two layer only) use and not very difficult. It will generate all data required for reliable production, and believe me, you do not want to handsolder TQFP1444 or TSOP devices! My MLDL2000 is professionally produced by an assembly house and is fully SMD, and without a CAD tool this would not have been possible.

Meindert


#17

Quote:
and believe me, you do not want to handsolder TQFP1444 or TSOP devices!

Actually they're pretty easy, unlike soldering the chip resistors and capacitors. Instead of trying to solder one lead at a time, you just put flux down the whole area, tack-solder a couple of opposite corners to hold the IC in place while you do the rest, and go down the rows soldering with the soldering iron tip as if you meant to make one continuous solder bridge. Then hold the board up vertically and go down the row again, and all the excess and bridging comes off on the soldering iron. It's ok if the iron tip is wide enough to cover several pins at once. It's rather quick to get a job that looks like it was done by machine. When you're done with the whole board, you wash the flux off.

#18

What are you using for level shifters? In my own designs, I usually use 74LVC parts as 5V CMOS to 3.3V CMOS buffers, and 74HCT or 74ACT as 3.3V CMOS to 5V CMOS buffers. For bidirectional signals there are some nice TI parts whose numbers I don't recall.

But there don't seem to be many parts suitable for level-shifting signals that can exceed 6V. The 74LVC parts are only rated for operation with inputs up to 5.5V. It appears that some vendors
74HC4050 parts can tolerate 13V inputs or more, but I haven't found much for low-to-high shifting.

I suppose some of the old CD4504B, CD40109B, and HEF4104B level shifters might be suitable for a 41C. They're really slow, but so is the 41C bus. These really old parts tend not to be available in parts smaller than SO, though.

Best regards,
Eric


#19

The output level shifters use individual n-channel and p-channel MOSFETs. The p-fet pull-up needs level-shifted drive, which uses an n-fet and resistor to 6V to make an inverter. The FPGA outputs true and complement data to simplify the external circuitry. This approach allows me to build the necessary logic in this "pad ring". For example, the SYNC output passes DPWO when the CPU is off. For the inputs, I was just going to use a resistive divider feeding a CMOS gate. The gate is to hold the FPGA inputs Low without loading the "real" 41C bus signals. I'll obviously need to breadboard this before committing to a pcb.

Monte


#20

Hi all. Hi Monte.

What is the expected size and cost of the finished unit?
Are you going to be able to retrofit it into a 41CV?
Am I missing the point entirely?
What sort of current draw are you looking at?

Very interesting design project...

Don W


#21

My intention has always been to build a drop-in replacement for the CPU board in a fullnut 41. I am doing everything I can, while keeping the design small enough to fit in the target FPGA, to minimize the current drain. But until I have a breadboard running it's hard to guess what it will be.

I haven't done a cost analysis yet, and it obviously is strongly dependent on volume. My target was $250, but it's too early to tell. I didn't go into this project to become rich. I mostly did it to dispell the myth that "it's too hard to translate the obsolete calculator CPU technology to a more modern implementation".

But what is a brain transplant for a 41 worth, bearing in mind that the transplant will hold nearly every 41 module ever made internally, have full x-memory, and RAM memory for a MLDL? Not to mention that it will run up to 50 times faster than the original 41? And are there more than three people on the planet interested in such a beast? I don't know.

Monte


#22

Sounds really cool, Monte...

I kinda figured you were doing that. But I just had to ask.
Well when you get it finished I want one...!

One question, though: Why did yu choose a clock rate of 50x,
not 64x? You must have your reasons and I imagine they are
very good ones.

Amazing project...

Don W


#23

The choice of 50x was fairly arbitrary, but I wanted something that wouldn't push the capability of the FPGA. Since I had never used this family before I set an arbitrary limit of 20MHz. Fifty times the original 41 operating frequency of 360KHz came out to a nice 18MHz. 64x would have been 23MHz.

Of course, since the machine uses BCD it seems more poetic to use something other than a power-of-2...

Monte

#24

Well, you can count me as interested!

#25

If you would even think of the slow 4000-series CMOS for level-shifting, how about using comparators like the LM339? Then you'd have static protection too, since they're not CMOS. You can set your input thresholds precisely, at any voltage you want, and the outputs can be pulled up a lot higher than 6V. (A brand new set of 4 alkaline cells will give you about 6.4V anyway, not just 6V.) I realize CMOS' power requirements when idle only consist of the microamp leakage current, but the comparators might offer a good solution depending on what you do with them and their pull-up resistor power when the calculator is asleep. You wouldn't need very many anyway, would you? I haven't studied the 41's innards to know if this is too off-the-wall, but I've used the LM339 for many level-translation jobs, including to continuously variable voltages instead of just set voltages like you'd have going from 3V to 5V and vice-versa.


#26

Hi all.

Well, Garth is right on with his tips for soldering smt.
I scrounge smt parts from old motherboards and have done
quite a bit of smt board component level repair...

On the level shifting question, yeah thats tricky but I think
enhancement mode fets might be the best bet if you can get parts
with the right on gate threshold? failing that yeah your standard depletion mde fets driven with inverted signals is the best bet
I imagine Monte.

The 339 is a really nice comparator. But they do draw about
200 uA per comp I think. I wonder if there is a real low power
or programmable ( adjustable chip Iset) quad or octal part out there somewhere?

Maybe a very low power cmos opamp with hysteresis would be
fast enough and have programmable Iset (I am thinking of some very old Intersil cmos linear parts but could bet they are gonna be way too slow. Maybe there is something more modern in the same vein?)

I have not thought this through at all but maybe you might
even be able to use a BIPOLAR transistor in common base mode.

I can't draw the ascii art in this form...

But you set the base at a threshold plus (about) 0.6 volts.
You pull down via a low value resistor on the emitter (of npn device) and the collector follows it down, but level shifted. Effectively open collector output ;-) Plus the collector comes right down to within the saturation voltage of where the emitter
is dragged... Current gain is about 1.00 ;-)

Probably would not work for many of the signals but maybe worth thinking laterally like that anyway. Fast too. Maybe for one or
two signals you can just shed volts by using a diode or two? IR led? Just a thought... Low parts count anyway.

Don W


#27

Quote:
The 339 is a really nice comparator. But they do draw about 200 uA per comp I think. I wonder if there is a real low power or programmable ( adjustable chip Iset) quad or octal part out there somewhere?

The LP339 takes less than 1/3 the power supply current of the LM339, but it's quite a bit slower too. But for logic-level-shifting, the open-collector arrangement has a big advantage over an op-amp-type arrangement. The down side in battery-powered applications is the power requirement.

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