Verilog or VHDL Emulator for HP 16C?



#7

I would like to build a model of an HP 16C using Verilog or VHDL (just learning) and was wondering if anyone could recommend resources to help me learn about the hardware architecture of this calculator?

Thanks

-- Bennett


#8

Hi, Bennett;

just to add that in either case, it's gonna be huge...

BTW, have you succeeded emulating the HP16C with a Verilog or VHDL script (I hope so), is there any chance that a custom IC is produced based on it? Maybe this is your main idea... That would be a "dream comming true", and changing the script so it emulates the other Voyagers would be, then, somehow faster and easier (at least for those who master VeriLog or VHDL).

And what are the chances that you can use the existing OS (provided it is available somehow) and emulate the HW core only? that would lead to an actual customizable IC... An HP16C with 999 program lines... better, with FFF program lines... an HP15C with 256 registers... Oops! My head found the roof...

Can you keep us updated with your achievements?

Best regards and good luck (to as all, in fact)

Luiz (Brazil)


Edited: 1 Feb 2005, 1:09 a.m.


#9

I understood there there is currently an attempt underway to create the HP41 processor in Verilog. This is the NEWT project which was presented during last years US HP conference. I do not know any further details nor the exact status. It would be great indeed if this would really work out.

Meindert

#10

... a team working on the development of RPN calculators, all of the basics plus final design (hardware/software, case, etc.). I tried to find their e-address but I could not find it, it seems I lost it the last "cleanning up" for viruses.

I guess they will soon post here.

Best regards.

Luiz


#11

The voyagers use the same cpu as the HP41. Resources for the HP41-CPU are easy to find. TOS might help you!

I wish you success, but keep in mind that emulation is only the beginning of work- hardware like case, keys etc are much harder to obtain unless the OPENRPN helps you!


#12

Klaus wrote:

Quote:
I wish you success, but keep in mind that emulation is only the beginning of work- hardware like case, keys etc are much harder to obtain unless the OPENRPN helps you!

Klaus is absolutely right. CPU selection + firmware is only a small part of making a calculator today. Costs of keyboard/keys, case/shell, etc. - esp nonrecurring setup costs - are the backbreaker. We like calculators and programming, so we naturally look to the chips/firmware first. Just like most carpenters think problems can be solved with hammers & nails ;)

VHDL/Verilog HP CPU is a fun exercise but would require a somewhat expensive EPLD/FPGA to run stuff on. Prob not the most power-efficient idea either for a battery operated calculator. Software emulation in a small 8 bit CPU, when done properly and with 'escape' layers to the non-HP outside world is gonna be way more productive, easier to implement, etc.

Bill Wiese

San Jose CA USA

#13

Thanks for the pointers everyone. It sounds like I need to start hunting for more information on the HP-41 processor first.

A bit more background on my goals.

I work for a company that builds simulators for debugging hardware designs. I am a software developer and need to build a hardware design using a Verilog like language that I can use as my test base for simulator improvements. I was thinking of the HP 16C since it is such a cool device and I have one on my desk that I use every day.

I had no idea that there was such a following for these older calculators. It sounds like there are people out here hoping that eventually someone can build a "next generation" version of these calculators. That may not be me, but perhaps the hardware design will be a start.

Does anyone know if there is microcode in the Voyager calculators or is all the functionality implemented directly in gates?

Thanks for everyone's help. I will keep you posted on the outcome...

Cheers

-- Bennett


#14

Quote:
Does anyone know if there is microcode in the Voyager calculators or is all the functionality implemented directly in gates?

You're kidding, right? I can't even begin to imagine how many gates it would take to build a hardwired HP-15C.

All the voyagers other than the 15C have a 6K*10 microcode ROM. The 15C has two of those, for a total of 12K*10 of microcode.


#15

I'm learning - having never built any piece of hardware before what do I know. This is why I am asking the questions. If I already knew then there would be no reason to ask. :-)

Since posting my original question I have learned about the microcode simulators/emulators you built, have learned about the newt microprocessor project, and more about the history of HP calculators than I ever thought I needed.

My goal is to produce a hardware design that I can use primarily to debug digital logic simulators. I'm not trying to do anything more than that. I figured it would be easier to build a logic design for a calculator than a typical general purpose processor and I was hoping that this would serve as a good, controlled test bench for improving an in-house digital logic simulator.

I really appreciate the help.

-- Bennett

#16

The 16C uses the same CPU as the 41C. What makes it a different machine is the software held in ROM. The specification for the CPU is available on the internet if you know where to look. Unfortunately it is not quite complete, so you have to make some intelligent decisions about how the designers implemented a few things.

Unfortunately, a similar specification is not available (at least that I have found) for the display driver chip. If you are ambitious and have the time, you might be able to figure out how it works by disassembling the 16C ROM code. I expect that it would be similar in many ways to the 41C display driver operation, and that spec is available on the internet.

The CPU is actually quite simple, and only requires 19 pages of Verilog HDL code. As Meindert mentioned in another reply, I am working on an enhanced version of this CPU so that I can do a brain transplant on 41Cs. It wraps additional logic around a Nut CPU core to add a number of new features. A preliminary specification for the NEWT microprocessor can be found at

http://www.systemyde.com/pdf/newt.pdf

Unfortunately I haven't had a lot of time to devote to this project since the HHC 2004 conference, but I expect to be able to run my first simulation within the next couple of weeks. Because I will be implementing this in an FPGA the power management will need to be done externally (so that I can power down the FPGA), and I still need to work that out. I intend to make that operation transparent to the user.

The other issue is the different voltage levels involved. The FPGA core runs at 2.5V, the FPGA I/O and memories run at 3.3V, and the 41C bus runs at 6V. I've got the 6V translators designed, but still need to design the power supplies for the remainder of the stuff.

I will post progress reports as I make progress.

Monte Dalrymple


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