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Spice series ROM self-test reverse-engineered



#9

I've mentioned here previously that on the Spice series (HP-3xE/C), the self-test uses a CPU instruction that reads an entire 1K block of ROM words (10 bits each, 10240 bits total) and computes some sort of check on it. Recently some email from Bill Weise prompted me to spend some time figuring out what exactly it is checking. The instruction seems to only provide a pass/fail result, and I'm not yet sure exactly how it indicates that.

Originally I thought it was probably computing a checksum, but I tried both a simple checksum and a checksum with end-around carry, and neither returned a constant value for every 1K block of ROM I've dumped.

Given that the calculator hardware works in an entirely bit-serial manner, it occurred to me that they might have implemented a CRC. Aside from guessing, I had no way to know what CRC polynomial they might use. I decided that the easiest way to find out would be to write a program that simply does a brute-force search by computing CRCs with all polynomials of orders 3 through 16 over two of the 1K*10 ROM page images. For any polynomials that compute the same CRC for both images, the program would then check the other images.

This program took about six minutes on an Athlon XP 1900+ system, and determined that the CRC polynomial is either CRC-10 (x^10 + x^9 + x^5 + x^4 + x + 1) or the reverse (x^10 + x^9 + x^6 + x^5 + x + 1). I'm not sure which because I find the definition of the CRC a bit confusing, since various references show the bits shifting in opposite directions, and the XOR happening on the input or the output side. But in any case, I now know how to verify a Spice ROM image.

More details including links to the code I wrote to do this may be found in my Advogato diary entry.

Presumably HP generated the ROMs by taking each 1K chunk of the assembler output (with one word of zeros reserved for the CRC, probably the last word), computing the CRC of first 1023 words, and storing it (or the complement?) in the 1024th word. A more complicated procedure would have been needed if they wanted to store the CRC in a word other than the last word.

I just realized that if the CRC word that needed to be stored in the ROM happened to be computed as 1060 octal, they wouldn't be able to use it, because that is the bank switch instruction, which is actually active even during the ROM selftest operation. So if the CRC did produce that value, they would have had to change the value of another word. Most of the time there was probably at least one more spare word in a 1K bank that they could tweak for this purpose.

I suspect that RAM write instructions are also live during the ROM selftest operation; there would have been little reason to make the RAM chips smart enough to detect the beginning and end of the selftest operation and disable writes. The logic would have been complicated, and they do a destructive RAM test anyhow.

If they'd tried to use the Spice CPU in a calculator with a printer, card reader, etc., they would have had to put some logic in the controller for those devices to prevent them from responding to ROM words read during the selftest that happen to be device control instructions. That may be one reason why they did not switch to the Spice CPU for later production HP-67 and HP-97 machines. That might also be why they removed the ROM self-test CPU instruction from the Nut CPU as used in the HP-41 and Voyager series.

On some of the Saturn-based calculators, they did add CRC hardware which is used for the ROM selftest (and for other purposes on the graphing calcs), but it operates under software control rather than as an automatic block CRC.


#10

Thanks for posting the article. That's a fascinating piece of detective work!

#11

I wrote about the Spice series ROM selftest instruction:

Quote:
The instruction seems to only provide a pass/fail result, and I'm not yet sure exactly how it indicates that.

Study of an instruction trace shows that they test status flag S5 after doing the self-test. It appears that S5 gets set if the ROM CRC is incorrect. Apparently it is sticky (doesn't get cleared for a correct CRC), because they don't always check it after the CRC check of every 1K block.

On the Woodstock-series hardware, S5 was one of the external flag inputs, along with S3. These were used for slide switches or other hardware status inputs. S15 is set when a key is pressed.

On Spice, S3 is still used as an external flag input for a slide switch, and S15 is still the key press flag, but apparently S5 is now not available as an external flag. It seems to be used for the ROM test result, but probably can be used for other purposes by the microcode when a selftest is not being performed.


Edited: 9 July 2004, 8:39 p.m.

#12

Eric,

This is pretty interesting stuff and very nice work!

I posted a message several years ago about a 38E that I have that fails the self test. After the failed test the registers contain strange values and I wonder if the these values give an indication of the block of memory that contains the bad checksum. Here's the post:

http://www.hpmuseum.org/cgi-sys/cgiwrap/hpmuseum/archv004.cgi?read=6147

#13

Hello Eric,

I'm not the expert of CRC calculation but I had a similar problem like you to discover the CRC polynom of the 1LR2 Lewis chip. I took me several hours without success because I thought the CRC build must be similar to the known one used in the Clarke/Yorke chip. The Lewis chip documentation was no help because the polynom wasn't described there. I'm a hardware man so I searched about techniques to build CRC' in hardware. It's easier for me to translate hardware into software than transforming a CRC polynom into software.

Here are the two hardware techniques implementing CRC's in chips with a Saturn core. All other calculators with different chips have no CRC generator in hardware. The XOR in the graphics mean that you have to XOR the bit content from the shift register before the XOR and the bit from the feedback.

--------------------------------------------------
- Lewis and Sacajawea chip CRC calculation stuff -
--------------------------------------------------

G(x) = x^16 + x^14 + x^13 + x^11 + 1

- Hardware implementation with 16 bit shift register

+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
D -> |0| |1| |2| |3| |4| |5| |6| |7| |8| |9| |A| |B| |C| |D| |E| |F| ->-+
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ |
XOR XOR XOR XOR |
^ ^ ^ ^ |
+-------------------------------------------+-------+---+-------<-+


-----------------------------------------------
- Clarke and Yorke chip CRC calculation stuff -
-----------------------------------------------

G(x) = x^16 + x^12 + x^7 + 1

- Hardware implementation with 16 bit shift register

+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
D --+--+--> |0| |1| |2| |3| |4| |5| |6| |7| |8| |9| |A| |B| |C| |D| |E| |F| ->-+
XOR | +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ |
^ | XOR XOR |
| | ^ ^ |
| +-->------------------------------+-------------------+ |
+------------------------------------------------------------------------<-+

Some general words to the hardware in the later HP calculators. The HP developers are also only cooking with water. I recognized that they really used very simple hardware constructs. Sometimes it happened in Emu48 that I emulated a hardware piece and I had one exception. Sometimes later I had to add a second or third exception to my concept and this was the time I was knowing my concept is wrong. Next step was thinking, when I have to do the job of developing this hardware under the bound of software is cheap and hardware is expensive, how I would do this? In most cases my solution and what I detected on the calculators are equal. That's not why I'm so good, it's the classic way to solve these problems. Furthermore the HP developers are very conservative, there are several solutions in hard- and software they copied from earlier project. Mostly every feature of the 1LP2 Centipede chip you can find in the later 1LR2 Lewis chip. Form the 1LP2 documentation a had a schematic from the IR-LED output pin, in the 1LR2 document this part was missing and really both drivers are equal.

Finally some words to the software part of CRC calculation. I especially speak here about the software part of Sacajawea and Lewis chip based calculators. As you thought in your MoHPC posting there must be a reference to compare the results of the CRC check with a reference value. On Saturn based calculators it makes no sense to add every xx KB a checksum because you always have to skip these checksums in program execution. So I wouldn't expect that you have a reference value in each 1KB block. In my case every physical ROM chip has one or two 16bit CRC's at the end of each physical ROM. These two CRC's are build by different methods and reading orders of the ROM content. Finally HP write not the result of the CRC check to the last address for comparing, they use the last 16 bit to adjust the content of the CRC register that it finally contain #FFFF as result of a good ROM image over the complete address area.

I hope this information helps you to continue your excellent work.

Regards

Christoph


#14

Thanks for the informative post about how HP implemented CRCs on their Saturn-based calculators. I have a few minor comments.

Quote:
All other calculators with different chips have no CRC generator in hardware.

Not true; the Spice series (HP-3xE/C) have CRC checking in hardware. When the instruction 1460 octal is executed, the CPU stops executing normal instructions, fetches 1024 words of ROM starting at the beginning of the 1K block the 1460 instruction was fetched from (unless the 1460 was the last word in the block, in which case it probably checksums the next block, but I haven't verified this), computes the CRC, compares it to a fixed value (residue), and sets flag 5 if there is a mismatch. Finally it does the equivalent of a return instruction, because the PC value was lost since the original PC was used for addressing the 1024 words. All completely hardwired. This is why an HP-34C with 7K*10 of ROM can do its selftest much faster than an HP-12C with 6K*10 of ROM, even though the HP-34C has a slower clock rate. In the HP-12C the ROM checksum has to be computed by software.

Quote:
As you thought in your MoHPC posting there must be a reference to compare the results of the CRC check with a reference value. On Saturn based calculators it makes no sense to add every xx KB a checksum because you always have to skip these checksums in program execution. So I wouldn't expect that you have a reference value in each 1KB block.

For most of the Woodstock-era hardware, the size of a ROM was 1K*10, so they needed a check value for each 1K. In the later Woodstocks and the entire Spice series, they actually had more than 1K per physical chip, but it was still logically organized as 1K pages, so they kept one check value per 1K page.

There is another reason for keeping the CRC block size small. As the block size goes up, the ability of the CRC to detect multibit errors goes down, but the probability of occurrence of multibit errors goes up. This can be countered by either using a higher-order polynomial, staying with a smaller block size, or using multiple, interleaved correction codes. Interleaved error detection or correction codes are very powerful, and interleaved Reed-Solomon ECC is used on almost all modern disks, both magnetic and optical. I think a form of this interleave technique is what you were describing when you wrote "These two CRC's are build by different methods and reading orders of the ROM content."

Quote:
Finally HP write not the result of the CRC check to the last address for comparing, they use the last 16 bit to adjust the content of the CRC register that it finally contain #FFFF as result of a good ROM image over the complete address area.

When you compute the CRC of the first [n-1] words, and store the CRC (or the complement of it) in the final word, that does force the CRC of the full block of n words to be a constant value, called the residue. In the case you describe, they arranged for the residue to be all-ones, but various systems use various values. For the Spice series, the ten-bit residue is 0x078.

For serial data transmission, it is common to start the CRC generator with the shift register initialized to all-ones, and to complement the final result. If this is not done, the CRC will not detect dropped (or inserted) zero bits at the start of the transmission. This is not paricularly necessary or useful for ROM checks, but it is still sometimes done.

One thing that I discovered with my brute-search CRC polynomical finder that surprised we somewhat was that there were both order-9 and order-10 polynomials that gave consistent results for all of the 1K ROM pages of all the Spice calculators (with the possibly but unlikely exception of the 31E and 33E which I have not yet dumped). The reason is that the order-10 polynomial is actually the product of the order-9 polynomial and x+1. If I understand correctly, use of a polynomial that has x+1 as a factor is advantageous because it guarantees that errors of any number of odd bits will be detected.

#15

You wrote :

"I'm not the expert of CRC calculation but I had a similar problem like you to discover the CRC polynom of the 1LR2 Lewis chip. I took me several hours without success because I thought the CRC build must be similar to the known one used in the Clarke/Yorke chip. The Lewis chip documentation was no help because the polynom wasn't described there. I'm a hardware man so I searched about techniques to build CRC' in hardware. It's easier for me to translate hardware into software than transforming a CRC polynom into software."

Just FYI, but the Lewis, Saca, and Bert CRC algorithms have been available in the GNU Hptools and official Hptools source code for years. Look in the file "sload/code.c" .

Regards,

Jonathan

-----------------------------------------------------------------

Jonathan Busby - jdb@SNMAPOhouston.rr.com


#16

Jonathan wrote :

"Just FYI, but the Lewis, Saca, and Bert CRC algorithms have been available in the GNU Hptools and official Hptools source code for years. Look in the file "sload/code.c""

Many TNX Jonathan, I wasn't aware that they must be somewhere because HP made all there later Saturn based machines with this tool. It's a little bit too late because I know them now and also made the table version by myself, but this solves another question I had.

The ROM check in the HP18C and HP28C is implemented as 4 nibble reading each, so I though that the checksum must be a 16bit word. SLOAD shows that it's only one byte at the end of each ROM block. I'll modify Emu28 that way, when the ROM is patched I patch the checksum also and you'll get a correct checksum for selftest. I done this already for the final version of Emu42.

Regards,

Christoph


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