Hi all,
I have to make some decissions regarding the final design of the NoVRAM module, intended to minimize the parts count...
Just to summarize for those not yet aware:
NoVRAM is a 16k (for now) RAM box in a standard HP-41 module enclosure.
It fully emulates the Advenced HEPAX module (including auto allocation in the lowest available page and RAM write protection) while provides two extra ROM pages, in a Clonix-like way
The question I'd like to poll you is about the automatic mapping ability of the Adv HEPAX. i.e. the 4 RAM pages are mapped to 8 - B if you plug the module into ports 1 or 2; or mapped to C - F if the module is plugged into ports 3 or 4.
I've been trying to figure out a good reason for keeping this feature in the NovRAM emulation (NoVRAM prototypes actually have it implemented), but so far it only takes some code space and requires two extra resistor for the B4 line sensing, and a somewhat more complicated PCB routing.
I've prepared a new prototype without B4 sensing (it always placed its memory in 8 - B pages, and have been unable to find any illegal configuration (appart from those stated in the HEPAX manual, which BTW have nothing to do with the mapping feature)
As I'm not one of those fortunate "real" HEPAX owners/users I'd like to ask you all if is there any reason for what such a feature should be preserved or not?
Thanks in advance.
Diego.
PS. I'll leave for holidays in a few hours, but will take a look to the 'net everynow and then.
Oh, Just a good news I've managed to re-shrink the code so the 6th page is again available!!