HP41 Bank Switching question


Thanks for the contributors for all the information about bankswitching, that has been very helpful. There is one more thing that I need to understand for correct implementation in my MLDL2000:

- I assume that the Enabled Bank setting in a ROM is forgotten after power down (Deep Sleep) and that Bank 1 of all modules is enabled when turning the HP41 on.

- What happens to the current bank in Standby mode? Is it remembered? If yes, how important is it? In the MLDL2000 I will probably switch the CPLD off when in Standby (use the PWO line to control the 3.3V regulator) to save power and the current bank is stored in a register in the CPLD.




Hi Meindert,

Here's what I've got to learn about Bank-switching (not too much, indeed):

You probably know already, but I'd like to remark that Bank-switching has nothing to do with CPU, they're NOP's. Thus, the only device involved in BS operations is the ROM PAC itself, it MUST produce it's own ENBANK (1-4) OP code, it must decode it, verify that this specific code points to the address page(s)** where this PAC is placed at, and perform the necessary hardware switching.

** When a Bank-Switch OP code is found, and its target page is determined (say for example H'9000) the port's companion page (say H'8000) is also switched.

Now to your question:

Is the Bank-Switching reset to BANK 1 on STAND-BY or SLEEP?

Not exactly, enabled bank is not affected by SLEEP/STAND BY transitions... but there's not need of such reset. In fact, looking at the HP *official* BS scheme as for the ADV PAC (other schemes exist i.e. RAM-Box and HEPAX) I've always found that it turns back to Bank 1 after Bank 2 operation completion:


Bank 1................Bank 2





BS2 Code ->...... Code

........................ Code...

Code......... <-BS1 Code





So you'll find Bank 1 enabled at such ROM PAC's whenever in Sleep or Stand-by.

Other schemes are manufacturer dependant and may (they do indeed) react in a different way. The RAM-Box referred above is a good example of unbalanced Switching scheme, and this *suggest* (haven't got a *real* RAM-Box to apply my probes to... :-(... and verify this, but the code is pretty straight forward and CAT 2 behavior -read below- is determinant) that the enabled bank 1 or 2 will also remain enabled while in Sleep/Stand-by. So, after performing a "PG10" command you'll see "RAMBOX b" on "CAT 2", even if you turn your 41 off and back on.

I have no info regarding HEPAX BS but apparently it follows the HP "standard" expanding it to 4 banks.

That means that you must implement different scheme behaviors depending on the the module(s) you're gonna replycate...

Please take what stated above as "to the best of my knowledge". I've collected this info as empirical observation on the modules behavior, during Clonix developement process.

A more "documented" advice will be of a great help to all of us :-)

Cheers from the Canaries and...

Meindert, keep the MLDL2000 wheel turning!!



Thansk Diego, as always your comments are helpful. My problem is that I can add hardware for powering down the CPLD even in Standby, but if it does not work, a redesign is required. I have done some tests yesterday controlling CPLD power with the PWO line, but need to do more testing.


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