HP41 Bank Switching & HEPAX Question

[Meindert Kuipers]

Now that the basic functionality of the MLDL works I am trying to figure out the best way to implement bankswitching in the MLDL2000 design. I would like to know if I understand the behavior correctly:

The ENBANKx (x=1,2,3,4) enable the relevant bank in the page the instruction is executed from. I assume that the behavior of the instruction is not defined for the system ROM's (page $0, $1 and $2)? Are there any other exceptions? In the source for V41 some exceptions are mentioned but these are pretty hard to implement.

I also assume that the two pages in a port (for example $8 and $9) are totally independent.

When in standby the state of the Bank Enable does not change? After Deep Sleep or Power Down the Bank Enable state of all ROMs returns to Bank 1?

Other question about HEPAX: it supports two extra instructions, one to write protect a RAM page and one to relocate HEPAX to an empty page. In the current architecture of the MLDL2000 these instructions cannot be implemented. Can anyone comment to the fact what would happen to the functionality of HEPAX if these special instructions (only used by HEPAX AFAIK) function as NOPs?

Thanks,

Meindert

[Diego Diaz]

Hi Meindert, folks,

First of all I must say I've been following your MLDL2000 work since the beginning, I have no microcontroller experience at all so I can't be of any help for you in that sense.

Anyhow, I'm quite handy with wires & chips (IC's... well... and fried potatoes also ;-) BTW I've just finished my own (breadboard-prototype) ROM Box, starting from the original Lynn A Wilkins MLDL as published in PPCJ V9N3.

I've done some modifications:

- As I was not interested in the RAM area, I rub the related components off.

- 2732 & 2716 pairs might be a good solution with '82 eyes, but nowadays, EPROM's are more easily found in bigger capacities and those older models are scarcy and non price competitive.

- Further more, the 10bit 41's word implementation in the original MLDL was extremely complex with 2 last bits (MSB's) multiplexed into an 8bit 2716 word for every four 2732 word... !? Well I simply place the 10 bits into two consecutive words of a 2764 or 128 or 256 or 512 (the last gives you the full 32k-words available for the 41's four extension ports) then read the Least Significant Byte from the odd address, send them to the ISA line, and at the proper time read the remaining two bits from the even address. So one only shift register is needed to drive the ISA line output and one only EPROM is needed to hold the "module" (or modules) data. Yes, you throu 6 bits away for each word but who cares?

- Several other minor "improvements" regarding the state counter and some gates saved here and there, and the whole thing is working.

Sorry, up to here I'm pretty sure I've told you nothing new, but I'm willing to share my experience so other can see that there is no mystery in bulding an (EP)ROM-Box for the 41.

Up to this point I've not implemented the bank switching capability for that, mainly because I have not a full knowledge about the way it works, but I've been doing my homework and here you are what I've found out:

- Bankswitching instructions ENBANK1, 2, 3 & 4 ($100, $180, $140 & $1C0 respectively) are NOP's for the 41 mainframe OS.

- Wichever module's willing to handle with them must reserve some specific memory addresses for the RETURNing, namely $XFC7, $XFC9, $XFCB & $XFCD (X beeing the hex value for the address four MSb's.

Address:..Instrucions

$XFC7:....$100, $3E0

$XFC9:....$180, $3E0

$XFCB:....$140, $3E0

$XFCD:....$1C0, $3E0

This MUST be present in every 4k bank of the module.

Obviously if a module is only going to handle Banks 1 & 2 it has no need to implement the corresponding returnings for Banks 3 & 4.

- Once the swithching has been performed, is in the internal module electronics in wich the responsibility of handling it relays, so the enabled bank is the one that can be seen at this specific 4k address area. This is why you can (e.g. in the HEPAX) relocate the address the module responds at, and override the "hardwired" B3 & B4 address lines to the I/O ports.

Remember this is an "at first glance" approximation of the bankswitching behavior, I've got a lot to learn about it yet and, of course, it may not be accurate in some points, so take it AFAIK and excuse me for the possible mistakes.

Some others out there sure can enligthen us with a deeper knowledge regarding this issue.

Cheers from the Canary Islands.

Diego.

[Jeff]

I have and can get any number of the 2716 and 2732 EPROM's. If you need some please let me know. Also, I am interested in redesigning the SRAM section of the MLDL as the TC5504AP-2 units are not available, as far as I know. I would like to find a one chip to do it all if possible. Any suggestions? One possible solution posted last week was to use an 8 bit SRAM chip in place of two 1 bit chips, and waste 6 bits (tie them to ground, perhaps through a resistor). Also, is there a way to increase the RAM on this unit to something more than 4K?
Jeff

[Diego Diaz]

Hi Jeff,

First, thanks for your offer about 2732/16 EPROMS, I also have a huge amount of them, but the main question is that using a single chip for the ROM data greatly simplifies de circuit. I think that earlier designs used that configuration due to excesive cost of 2764 or 27128 chips circa '82 (only a guess).

Regarding the RAM question, the same rule is applicable, TC5504AP-2 must be almost impossible to find and are by no means recomendable for a new design. In my opinion you'd better try the previous thread advice, take any 8bit low power static RAM in the market and multiplex the access for the lower 8 and upper 2 bits.

Of course you can place as many 4k words pages as you can, provided you have no other modules in the same address space, wich means that you can have as much as 32k words of RAM space with all four I/O ports address space available (even 40k words if no other peripheral is connected as you can also use Pages 6 & 7). So you can accomodate two 16K bytes RAM chips (e.g. HM65256 or the alike).

Nevertheless you must save some space for the RAM read/write routines wich must be present to alow the use of said RAM.

Hope this help.

Kind regards.

Diego.

[James]

Quote:

---

... redesigning the SRAM section of the MLDL as the TC5504AP-2 units are not available, as far as I know. I would like to find a one chip to do it all if possible.

---

A quick look through DigiKey shows there are 16 bit wide SRAM chips available from Cypress, but they are in awkward packages (TQFP etc.), and it
looks like the low power 16 bit SRAM only comes in low voltage versions (<= 3.6V). (You don't want a fast SRAM, as you couldn't run it off
batteries.)

eg. go to http://www.cypress.com/ and click MicroPower SRAMs.

Toshiba has some low power 5V 16 bit SRAMs, also in awkward packages:

http://www.toshiba.com/taec/cgi-bin/display.cgi?table=Category&CategoryID=232

eg. TC554161A,-L, 256K x 16, 5V 54 pin TSOP II: http://www.toshiba.com/taec/components/Datasheet/554161a.pdf

However, even if you can find a single chip part, I would avoid going this route... the more exotic the part, the harder it is going to be to get (more) in
small quantities, and the more it will cost. Generic 6264 (8K x 8) parts are going to be available at a good price for ages.

HTH,

James

[Meindert Kuipers]

Get the biggest SRAMs you can get. The usage is all defined in your address decoder and you can always tie unused address lines to zero. I would not take 16-bit SRAMs, these are somewhat exotic.

I have just posted pictures of my breadboard prototype MLDL2000, and that uses a 4 mbit SRAM. This was not available in DIL, so I soldered a little board together(just do not drink too much coffee ;) The picture location is at

www.kuipers.to/final%20for%20web/original/P5200175.jpg The empty socket is for the FLASH Eprom, which was not available in the SO32 package

Problem today is that most of these parts are all 3V.

Consider FLASH Eproms instead of the classic. Programmers are cheap (unless you already have one) and fast and you do not have to spend 20 minutes erasing them under UV light.

Meindert