MLDL2000 - update (long)



#7

As some of the regulars here will probably know, I am working on a project to develop a combination of Rombox and MLDL for the good old HP41. As development is now coming to a stage where there is some outlook to an actual prototype I would like to exchange information in a somewhat different way by starting a mailing list to keep all interested up to date with what's happening.

To subscribe to the mailing list please send an email to majordomo@kuipers.to with in the body the text: subscribe hp41_dev. To post a message simple send email to hp41_dev@kuipers.to. Note that only subscribers will be allowed to send messages to the list.

Let me know if you do not like this way of communication or if you rather prefer this forum.

The MLDL2000 is a non-profit project. All information will in the be available to the group under the GNU license: schematics, PCB layout, VHDL sources, specification, CPLD programming file. I will even use free tools as much as possible to accomplish all this. Most information is already available at www.kuipers.to/hp41.

Functionally, the MLDL2000 will store up to 47 (!) ROM images in Flash Eprom and up to 11 ROM images in SRAM, that can be edited at will with a suitable program. Bank switching will be supported and the MLDL2000 will have a simple interface to the outside world to allow up- and downloading of ROM images, programming and erasing Flash and to some extent data exchange with the HP41. For detailed specifications please have a look at www.kuipers.to/hp41

As I currently see it I will supply a PCB mounted with components and programmed CPLD. I will probably not supply the housing and/or the HP41 connectors. The PCB will be small enough to fit in a card reader housing. The CPLD with all the logic is reprogrammable in the field to add features or to fix bugs.

The project is far from finished, but proceeding nicely. No hardware is prototyped yet, but simulations show succesful access from Flash Eprom and SRAM, including the '040' WROM instruction. This leaves the external interface and bank switching to be implemented. I intend to start prototyping a simple rombox within a few weeks to prove interoperability with the HP41.

I would like to call for help for the following:

- PCB layout, prefreably in CADSOFT Eagle

- hardware design issues: 5V-3.3V conversion, supplies

- specifics on HP41 bank switching: need some more detailed info

If you think you have something to offer, please contact me!

As usual, comments are welcome!

Meindert


#8

Hello, Meindert;

I wish I have more knowledge to help the way I'd like, but for now I can only research the power supplies.

Would you send me the specs and limiting factors? I mean

- input (or available) voltage
- input voltage characteristics (battery type, recharger circuit or not)
- output/needed voltage(s)
- load characteristics (current demand OR what is the load)

About the fourth item: possibly you have the FLASH writer, memory IC's, controler and a few other devices. Steady current consumption is the most desirable situation, and in most cases you may design a power supply based on this particular assumption. Anyway, if you have some sort of load that has variable power consumption, it must be considered to avoid power loss. If your input voltage comes from batteries, what sort of batteries (and in which number) you intend to use: rechargeable or not? Or you think it's better using the very own calculator batteries?

Have you already thought about this all? As I think you're dealing with logic design a lot more than electronic design (I'm downloadig your updated files later) maybe you did not thave the time even to think about these.

I'll try the best to help wher I believe I can.

(Calling Captain Zener; calling Captain Zenenr... did he let any speciall call device with somebody? PLease, tell Norm I'll need some analog advice here...)

Luiz C. Vieira - Brazil


#9

Luiz and others,

Power requirements for the MLDL2000 are pretty simple. I do not expect it to draw more than 1 mA, probably even half of that. The CPLD, Flash and SRAM all run at 3.3V. A simple regulator will derive that from the HP41 battery. SRAM could be protected by a small cell when unplugged, but nothing rechargeable is planned.

Flash programming requires most power, but I will specify that that works only with the HP41 connected (I need the 41 clocks anyway).

My biggest challenge is hooking up the Xilinx CPDL (XPLA3 type) to the HP41. All I/O for the CPLD is 3.3V, but 5V tolerant, with a max at 5.5V. This means that HP41 I/O's will be too much, and a converted is required here. Driving the HP41 from the CPLD is another difficult point, but can be solved using an external CMOS driver circuit connected to the HP41's supply. There are some tricks to make the 3.3V CPLD talk to that by. There are only two lines to be driven that way (ISA and DATA) and the additonal power consumption is not that much.

You are totally correct that I am a digital type, but I am learning.

Meindert


#10

Meindert,

I think it is not a real problem to hook the CPLD to the
supposedly 5.5V outputs of the HP-41. The whole issue with
the 3.3 vs. 5 V is that the threshold values for Low and High are setup in a way (IIRC 0.4V/2.0V) that they are
compatible to standard LS-TTL. A driving LS-TTL will usually exceed the High-Threshold (it could in theory infact drive
5 V or more), but the CPLD contains clamping diodes in the
IO buffer element that will limit this to the CPLD supply
voltage. If you want to be on the safe side, just add a
5V1 Z-diode to each CPLD input connected to the HP. There are some converters from CMOS to LVTTL (that's what the 3.3V
TTL is called) but this appears overkill to me (besides you
need some additional logic for the ISA line to switch direction - it is bidirectional. In the Xilinx docs you can
BTW find some paper that explains conversion between CMOS and LVTTL.

Holger


#11

Here comes Captain Zener again ...

Holger, I think you are correct. Note however that the HP41 power with fresh batteries can exceed 6V. Driving ISA (or DATA) is actually more tricky I think, and I did go through the Xilinx doc. Normally I could use a pullup to 5V for a logic high level, and not drive ISA for high levels, and drive low for low levels. The problem is that the HP41 expects ISA low when idle (reading zero means nothing is connected), and that means I would have to drive ISA low all the time and that creates a problem on this bi-directional line if something else is driving this.

The only solution I see is with an external driver, while the CPLD has an ISA_in, ISA_out and ISA_enable for enabling the output driver (same for DATA). I you have another way around this let me know, but the logic is not that complicated, just requires an extra component (which might be needed anyway for 3.3-5 volt conversion).

Driving TTL would be less problematic, but driving the HP41 CMOS under the steady state level would draw more current (though only for a short time I must admit). I am preparing some experiments to see how this can best be solved, but I am certainly open for your input!

Thanks,

Meindert


#12

the CPLD contains clamping diodes

Normally, I would try to avoid this sort of voltage limiting due to the battery power wasted, but I admit that has to be weighed against development and manufacturing resources.

I also worry that clamping will affect other modules on the bus that expect CMOS levels, causing them to malfunction when the bus signals are clamped to ~4 volts.

Perhaps the first prototype can reveal if this is going to be a significant issue.

James


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