MLDL FPGA updated


NEW: The first version of the FPGA MLDL solution is now more or less finished. It is actually the first step and is a VHDL description of a ROMBOX, supporting 8K of ROM (2 ROM modules) plugged into a HP41C port. I believe it is fully functional, but I am working on refining the testbench as a preparation for a fully functional MLDL with all bells and whistles. IMPORTANT: I have not built the hardware (yet), all is based on simulations! I plan to setup some hardware exeriments when I get some feedback from you and when I have a better idea of how large an FPGA/CPLD I will use.

I am using the Xilinx free ISE WebPack 5.1i environment (free after registration) which is a great tool with a very good simulator (ModelSim). The free version has some limitations but I have yet to encounter one.
I have put the VHDL sources of the ROMBOX and testbench on my website: and are awaiting your comments!


I also posted a PDF of a simulated ROMBOX operation with all signals, just found out how to do that from Modelsim!


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