Re: Power management and deep sleep


Yeah, I'm familiar with what can and can't be done with the current ARMs. I am just feeling more interested from a historical/technical/personal interest.

Aside from the CMOS implementation the effective cpu cycle
time is quite slow which contributes to the reduced power

In normal running mode the cpu LC oscillator is enabled,
ISA bus clocks, control, and data are active, and the cpu
is continuously executing instructions. The LC tank
oscillates at ~880KHz for a voyager with an internal 4x
divide to produce the base ~220KHz clock and the resulting
56bit 3.9KHz ISA bus cycle time. Pretty sluggish but given
the application specific architecture the actual processing
throughput is equivalent to what a contemporary general
purpose processor can perform at 1-2MIPS in emulation.

The voyager firmware as an example doesn't spend too much
time polling for user input before it times out and powers
off the CPU, halts the LC oscillator, an idles all bus
signals. In this mode the LCD controller is still
driving the display clocked by an internal RC oscillator.
Seemed a bit unconventional to find this timeout pushed
into the display controller but it is quite sensible as
it allows the cpu to be fully quiesced. And the 10m
sleep timeout can then be clocked by the display RC oscillator
at a far more power conserving ~500Hz.

Contemporary SoCs have sophisticated power management
schemes and support power down of functional subsystems
independently. But I find the NUT cpu design quite
interesting, particular considering the relative infancy
of VLSI design in 1978.

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