Re: Power management and deep sleep



#2

Tim,

For the 41CL I had to mimic the power-down modes of the original 41C series as best I could. I think I ended up with something quite similar to what was used. Basically there are three states: Deep Sleep, Light Sleep, and Running.


In Deep Sleep power (Vdd) is shut off to the majority of the logic, which in the 41CL is a Flash-based FPGA. The program storage, also being FLash, is powered down, and the main voltage regulator is shut off (it still passes the unregulated battery voltage), along with the master oscillator. So the only things drawing power are: the static RAM (data storage), the CPLD (which has the wake-up logic), the RS232 chip (just in case in the future I add serial wake-up functionality), the micro-power regulators for the RAM and CPLD, and two resistive dividers in the main power supply (one for the low-level detect, and one for the voltage-level feedback).


Light Sleep is the state where the calulator is "on" but not actually doing anything. Everything is powered, but static. The oscillator is still running, but the clocks are stopped inside the FPGA. Because of the way the keyboard scanner works, all of the column drivers have to be Low in this state (to detect any keypress), but that is a slight problem, because the column signals are really open-drain drivers with resistive pull-ups. So the pull-ups have to be as large as possible. But this conflicts with the timing for the keyboard scanner. What I ended up doing was during the actual keyboard scan, precharging all of the column lines before actually driving one of them. This allowed me to use megohm pullups instead of the 75K that would have been required to meet timing. That saved 370uA during light sleep.


I guess the bottom line is that when going for low-power, try everything possible, because it all adds up in the end. The 41CL current drain isn't as low as it could be because the programmable logic vendors haven't really cared about power. I mean, the wake-up logic required to remain powered is perhaps a dozen gates, but the CPLD draws alomst 100uA. If I were doing this in a custom chip that number would be less than 5uA. Even the resistive dividers in the power supply is a trade-off. I live with 3-4% accuracy on the voltages, because that lets me use higher-value resistors, saving another 10uA or more per divider.

Monte


Possibly Related Threads...
Thread Author Replies Views Last Post
  Deep Drawn Aluminum Sources Hugh Evans 11 478 11-22-2011, 02:24 AM
Last Post: David Griffith
  Re: Power management and deep sleep uhmgawa 0 103 01-21-2011, 07:55 AM
Last Post: uhmgawa
  Power management and deep sleep Tim Wessman 7 304 01-09-2011, 05:09 PM
Last Post: Christoph Giesselink
  Updated DATA management (STAT & DATA) Geir Isene 10 413 11-21-2010, 04:18 PM
Last Post: Geir Isene
  HP-41 File management system Geir Isene 4 223 11-21-2010, 02:57 PM
Last Post: Geir Isene
  HP SmartCalc 300s - How deep...? Joerg Woerner 10 573 01-23-2009, 04:59 PM
Last Post: Joerg Woerner
  Newbie Stack/Memory Management (33s) Adam Price 0 107 02-27-2007, 06:24 PM
Last Post: Adam Price
  deep cycling NiCad N cells db (martinez, ca.) 8 356 02-12-2007, 12:21 PM
Last Post: Richard Ottosen
  PC power > HP-calc power, yet... $PC = $HP48gx ECL 7 353 12-03-2006, 08:04 PM
Last Post: Tim Wessman
  HP 17bii+: Financial Management Rate of Return (FMRR) Question E 7 348 09-01-2006, 05:47 PM
Last Post: e

Forum Jump: