Posts: 275
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Joined: Mar 2010
For the CPU it's not done from the software emulator code. It's based on the hardware description of the system in an HP patent. The described microcoded machine is coded in verilog.
Actually it's running at real speed (625 kHz) for debugging reasons but the actual code should run at x4 speed and perhaps at x10 which is the maximum this board could achieve (50 MHz base clock with 110 ns RAM). As the cpu can access to memeory every cycle, the limit is the RAM speed (plus some timing delays).
In fact a pure software emulator could be faster but not as energy efficient :) (2 GHz system to have x50 speed)
The IO system is more based on the behavior from the software emulator which is enough to have a running system.
For other architecture, I don't know if the hardware description is detailled enough to permit this kind of emulation.
Olivier
Edited: 27 May 2010, 1:09 a.m.