all,
"inspired" by raymund's current thread on the HP-71B bus simulation, i thought it might be in order to leak some information on my two current HP71-B ram extension projects. (obviously, i am not the only one in this forum living curiosity with a logic analyzer..)
1) so far, i managed to successfully link a cypress 256 kByte SRAM to the bus, giving a total of 128 kByte usable RAM (because in the current development stage, only 1 nibble per byte is used). the whole thing easily fits into a front port module.
2) next step is to use a 512kByte FRAM instead of the SRAM and pack it into a card reader housing. the completed memory module will feature 16 user-configurable ID-registers, each defining a 32kByte block of the FRAM as either RAM or write-protected RAM(ROM). i am currently working on the logics for a nybble-to-byte merger (and byte-to-nibble splitter) in order to make the complete 256kB (512kB) available.
the hardware is realized with an actel igloo FPGA and is still in a very early stage, but the design looks promising and might be useful to link any 8-bit parallel device to the 4-bit HP-bus. -->feature requests are welcome!
best regards,
hans