HP71B - Bus



#10

Is there any experience with HP-71B Bus measurement with a Logic Analyzer? Screen dumps?

Thx

Raymund


#11

I know it is not what you asked for, but what do you want them for ?
I made some measurements with a LA of the HP-71B bus for a RAM expansion board I made last year, but it seems, now that I look for them, that the files are gone :(.
The BUS is described in the hardware manual for the HP-71B (it is in the museum's CD collection). I can make the measurements again, it is not a problem.
If you plan on some hardware I'd recommend you use level shifters (like the 1T45 from TI) because the voltage swings from 0 to 6V outside the commonly-used-today CMOS chips. (Unless you use the 4xxx series, of course).


#12

Hi Alejandro

I have created a "Software" HP-71 Bus and as a feature I think about a "Logic Analyzer" function presenting the HP-71 Bus signals.

So no Hardware.

Does the Bus description in the IDS match the reality?

Thanx and BR

Raymund


#13

Yes it does. I can post a trace image if you (still) want it. What is your program for ? Are you writing an emulator ? (No problem if you do not want (yet) to tell).

#14

hi raymund,
i am currently working on a RAM extension, too. i did some investigations on the HP-bus and it works very well according to the hardware IDS, chapter 2.1., 2.2, 2.3. i did not test 2.4. yet.
chapter 2.3.data transfer implies that single nibble transfers are possible, but i was never able to catch one in real life. maybe, someone (you?) can shed some light on as to whether there *are* single nibble data transfers, or always bytewise data transfers on the bus.

best regards,
hans


Edited: 8 May 2010, 2:26 a.m.


#15

Quote:
chapter 2.3.data transfer implies that single nibble transfers are possible, but i was never able to catch one in real life. maybe, someone (you?) can shed some light on as to whether there *are* single nibble data transfers, or always bytewise data transfers on the bus.

Hello Hans,

some PC addresses of ROM 2CDCC where the OS doing single nibble transfers. Behind the opcode I added the content of the data register at this time. All captures are made during the BASIC command line waiting.

0070A   C=DAT0  1       D0=#2F6E3
0EF86 C=DAT0 P D0=#2E1FD
0EF90 C=DAT0 P D0=#2E1FD
014CF DAT0=C 1 D0=#2F81F
0150D C=DAT0 S D0=#2F81F
01B71 DAT0=C 1 D0=#2E3FF

Cheers

Christoph


#16

christoph,
the reason why i was asking is as follows: *if* it would have been a simple bytewise "affair" it would have been easy to collect two nibbles from the bus in a single 8 bit latch and then write the data in one step into a bytewide RAM. however, if there is a nibble-wide piece of data to be stored in RAM, then one has to a) read 1 byte from RAM into latch, b)modify contents of latch with previously read nibble, c)write back byte in latch into RAM.
thus, the "1 nibble scenario" requires more process-cycles than the "always 1 byte scenario".
schade eigentlich. aber danke fuer die info!
best regards,

hans


#17

Hans,

there's a more worse scenario: writing a byte to an odd Saturn address!

When you have a look onto the Yorke chip signals inside the HP48GX you always see two read cycles when you write a byte to an odd address in RAM.

Life is hard. ;-)

Cheers

Christoph

#18

Quote:
I made some measurements with a LA of the HP-71B bus for a RAM expansion board I made last year, but it seems, now that I look for them, that the files are gone :(.
Would you mind sharing your experiment results on this RAM expansion board for the HP-71b? Any picture or design details would be greatly appreciated !

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