Did someone say that Advantage cannot be loaded in NoVRAM? Was it me?


Hi all,

Sometimes, as you're trying to explain any particular concept you're supposed to know, to someone who's interested in the subject; your brain tries to find some reasoning path in order to make the concept more easily understandable.

Under certain circunstances this leads you to either extend or change your focus on this especific issue and, suddently, you realized that there are a whole new range of possibilities you haven't even conceived before.

Sorry for the long introduction. It comes to the point that, as I was trying to explain (some posts below) the deeply fundamented reasons why Advantage .ROM files *cannot* be used altogether with HEPAX emulation into a NoVRAM module, I saw a small light comming from a narrow gap in my explanation.

Certainly, HEPAX need 4 pages, Advantage needs 3: total 7. NoVRAM has only 6 ROM pages, conclusion: Advantage cannot be burned into NoVRAM's ROM. Period.

Second argument, Advantage is bankswitched, HEPAX RAM does not support bankswitching. Advantage cannot be loaded into NoVRAM's RAM either. Period.

Small gap: *Only* the upper page of Advantage is bankswitched...

And, what if?... we load that lower page into RAM which is not bankswitched... (who cares?) but it IS (and more relevant) *Non-volatile*, placing it into page C at first instance and then COPYROM to page A.

After this, another burning process is required to place both bankswitched images of Advantage's upper page into page B bank 1 and bank two respectively.

Originally page B is reserved for RAM, so I wrote a modified version of the NoVRAM code for that purpose. This sacrifies RAM pages A and B in order to gain the required space for the Advantage images.

Page A is still RAM from a phisical point of view but it's seen like another ROM (not bankswitched) ROM page.

In abstract we get a Standard HEPAX (with 8K RAM) + Advantage into a NoVRAM, using pages 8 to C, and one single physical port.

The process is not the most straightforward, but.. IT WORKS! ;-)

And, sincerelly, I've enjoyed a lot...

Best wishes from the Canaries.



Brilliant! I would very much like to do this. IANS, HEPAX and Adv Upper pages in ROM and the lower page in RAM. Then there are 3 free RAM pages that can be used for anything? In the remaining 3 I'd like EXT I/O and PPC (total of 3 pages). Can that be done too?


Edited: 14 Sept 2008, 7:12 p.m.


Hi Egan,

And thanks for your kind words!

According to HEPAX manual, and its functionality, RAM pages must be kept all-in-a-row, that's why it's required to remove the two RAM pages corresponding to port 2 (A & B).

Attempting to overcome this limitation, by relocating the horphan RAM page beyond the 8-B 16k limits (i.e. page C) will require a new design concept which is far beyond the scope of this utility.

Sorry for the bad news. To compensate, I've placed the required tools and a brief guide here.

Hope you find it useful.

Best wishes.


P.S. Please consider both the method itself and the related files as purely experimental. They have not been tested beyond CAT 2, HEPAX 002 and inverting a simple 2x2 matrix using 'MATRX program from Advantage.

Edited: 14 Sept 2008, 8:22 p.m.


Is it possible to set up the NoVRAM so that the one RAM page is not wasted?

Setup such as this:

16K ROM 'standard' Hepax auto addressing.

8K ROM bankswitched Advantage upper pages in page D.

4K RAM addressed to page C (may have to be initially loaded while addressed to page B, and then readdressed to page C afterwards, perhaps by post configuration addressing change without disturbing contents?)

12 K HEPAX RAM memory in pages 8,9,A

(Page B left null)



Hi Dan,

Regrettably no, (and this time there is no ligth comming from gaps in my explanation... :-)

Adv HEPAX RAM memory can only be mapped to a "straight 16K block", meaning 8-B or C-F. (NoVRAM just doesn't care about the C-F option because it always assume to be plugged into ports 1 or 2.)

The reason behind that is the RAM memory is physically implemented into a single chip (both in HEPAX and NoVRAM), and splitting the addressable range of a single chip requires a huge software overhead which can not be fitted inside the tiny 2048 bytes code area. Even if there were enough memory for the code, the remmaping process itself won't fit the tight timing requirements of HP-41 I/O bus.

Again sorry for the bad news, however, hope you can enjoy this new configuration despite of its limitations.

Best wishes from Spain.




Although the preliminary release of the NoVRAM+Advantage emulation is fully operative at user level (as far as I've been able to test), there are a couple of issues that I've improved. They don't affect regular use... but some users here don't fit into the "regular" category... ;-))

A) Write protecting page A: Remember that page A is loaded into RAM, so it could eventually be overwriten and corrupted. To avoid this possibility the new update keeps page A permanently protected. No write command or CLRAM will affect it.

B) This is for those with curious minds... (most of you?): The HEXEDIT command allows direct operation by reading/writting at the word level. It also allows editing a bankswitched page and navigate across its different banks. You'll notice that a page is bankswitched because flag 1 will be set indicating the Bank 1. To change the Bank just press [+] or [-].

While in normal operation bankswitched modules does not interfere among them. HEXEDITing is a very special (unique?) situation in which one bankswitched module (HPAX) directly operates with another bankswitched module.

As both modules share the same bankswitching scheme into NoVRAM emulation, trying to change to bank 2 while HEXEDTing page B (the bankswitched page of Advantage, returned NONEXISTENT.

A new implementation with separate bankswitching schemes for HEPAX (1 to 4) and Advantage (1-2) has also been included in this update in order to allow full HEXEDITing of page B banks 1 and 2.

The new update can be downloaded as usual from here.

Hope you enjoy it!

Regards from Spain.


Edited: 17 Sept 2008, 6:00 a.m.

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