This is something that has bugged me for a long time, I believe since I bought my 16C back in the 1980’s. It has to do with the behavior of ISG and DSE. Consider the BASIC loop:
This corresponds to setting I to 1.004 (on a 33s and, presumably, 35s) and doing the ISG at the end of the loop. The loop executes exactly 4 times, as you would expect.For I = 1 to 4
Next I
Now, consider this BASIC loop:
This corresponds to setting I to 4.000 and doing DSE at the end of the loop. You can’t make it 4.001 (which would be consistent with ISG) else it won’t do the last loop iteration you want.For I = 4 to 1 step –1
Next I
I think that if DSE had been implemented as “DSL”, then ISG and DSL would be consistent and would work as in BASIC. But since DSL has another meaning these days, oh well.
Am I the only person in the world bothered by this? There are times when I wanted to loop down and have the final loop iteration be index 0, but that is not possible without manipulating the index within the loop, and the whole point of ISG/DSE is to not have to do that, right?