Help please!!!! 41CX Time chip commands and registers



#2

Hi All!

Help please!!!!
I make emulator of 41C/CV/CX, and i need detailed explanation Time chip commands and registers.
Thanks for help!.
ZOleg


#3

He-e-e-e-elp me please!!!


#4

I've found a little bit of data on the time chip. It appears to consist of 2 timer/alarm circuits (called 'A' and 'B'), each consisting of a time counter, an alarm register and a scratchpad register. All are 56 bits long as you might expect, and communicate with the CPU via the DATA line (and thus via the C register).
The time counter is incremented every 0.01s. An alarm is generated if its contents are the same as those of the alarm register. The scratchpad is just that -- 56 bits of storage.
There are 2 other registers in the chip, the status register and the accuracy factor register. They both apply to both timer channels, but the status register is addressed as part of channel A and the accuracy factor as part of channel B.
Now, as for the commands (all given in Octal). To select the timer chip, you use the instruction 1760 with the peripheral address 0xFB in the C register as usual. The 'Enable data storage' instruction 1160 will disable the timer chip
And the PWO Off instruction 0140 will cause the timer to keep running, but will not attempt to synchronise it to bus cycles (which is what you'd want if the machine is turned off).
1750 sleects channel A, 1650 selects channel B. Now for the channel-specific commands :
0050 writes the C register to the clock timer count register. 0070 reads that register to the CPU's C register. 0250 writes the C register to the alarm register, 0270 reads the alarm register.
0350 wrtites the status (or accuracy factor) register, 0370 reads them
0450 writes the scratchpad register, 0470 reads it.
There is also a 5 digit (nybble) interval timer, which cna be used to generate alarms every 0.01s to every 999.99s. 0550 writes and starts the interval timer, 0570 reads it, 0750 stops it.
1050 clears the test mode flip-flop, 1150 sets it (there are 2, one addressed as part of each channel, the standard mode is with them both clear).
1250 disables alarms on the selected channel, 1350 enables them, 1450 stops that channel from incrementing, 1550 starts it.
As you may have guessed by now, the clock timer counters and alarm registers are in BCD, in 0.01s units. Only the bottom 13 bits of the status register are used. Bits 0-5 can be read or written, bits 6-12 are read only. The bits have the following meanings :
0 : Alarm A matched, 1: Clock A had incremented through 0, 2: Alarm B matched, 3: CLock B has incremented through 0, 4: Interval timer has incremeted through 0, 5: Clock has powered up after losing power
6: Clock A enabled and running, 7: Clock B enabled and running, 8: Alarm A enabled, 9: Alarm B enabled, 10: Interval timer enabled, 11: Test mode A, 12: Test mode B. The time chip also drives the CPU flag input line (nothing to do with user flags). It generates flag 12 and flag 13 when an alarm goes off, basically. That should get you started, anyway.


#5

Thanks to all for help!!!


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