PPC MLDL Project

Recently I began a project to produce the MLDL discussed in the PPC Journal. I have had some success and some failure with the Phase Counter portion of the PPC MLDL. I have narrowed it down to 4 wires that cause problems. Whenever I connect the SYNC to the Phase Counter at the CD4013 pin #5(data), this locks the calculator up. Also, whenever any of the three ground wires are connected to the same IC, CD4013, pins 4,8 and 10 this causes the calculator to phase out, display fades away and then the calc locks up. Any thoughts to this. I have connected everything else up and it seems ok. Also, if you look at page # 35 in this documentation and see the BAT, V+ and GND connections on the cable connector. Then look at page #28 They show the V+, VCC switched from the cable connector. As long as this is how they are connected it is ok but I thought that the V+ and VCC might be mixed. Any thoughts from the HP Community?


Please remind me what issue(s) of the PPC Journal so I can look it up on Jake Schwartz's CD-ROMs!

When the calculator display fades out, has the supply voltage fallen? You mention ground wires on a chip - on CMOS chips, all unused inputs need to be connected to GND or VCC (or a logic level) but not left floating, worst case both transistors on the input circuit can turn on and the chip draws excessive current - maybe enough in this case to pull down the power supply.

Because of the protection diodes on all inputs of CMOS chips (clamps to VCC and GND), and the low current requirement of the chips, input signals can be rectified and supply enough current to power a chip - maybe marginally - if the chip's VCC or GND pin is open.


PPC Calculator Journal V9 N3.
Your help is greatly appreciated. There does not seem to be any mention in the documentation regarding the comments that you have made. I am assuming that it is left to the reader to have the full understanding of the CMOS chips. Please take a look at the circuit and let me know what or how you might wire this.
Best Regards,


Now that you have given specific information regarding your problem with the PPC MLDL design, I'll try to give you some suggestions.

First, the comment about CMOS inputs being tied to ground or supply - that is correct, as is the comment that I.C.'s with floating inputs can draw EXCESSIVE current. In fact, ground is the preferred referance/connection in most designs. And my understanding of the port connections is that (looking INTO the calculator port, out of the MLDL plug, or INTO the BACK of the plug) Vbat is the first connection on the left, followed by B4, Vcc, B3, GND, PWO, DATA, FI, ISA, SYNC, 02, 01. Vbat is the battery voltage (RAM sustain voltage) and Vcc is a higher voltage generated by a power converter inside the calculator which powers the active/operational circuits when the calculator is turned on. They are not the same. Don


Check out page 32 of the PPC Calculator Journal V9 N3. In this Phase Counter diagram, U1 (4013), Pins 3 and 11 are connected to 01. Pin 5 is connected to SYNC. Pin 6 is connected to the output from U19. Pin 1 is connected to Pin 9. Pin 2 is connected to pin 6 of U19.Pin 13 is connected to pin 5 of U19. Pins 4,8 and 10 are connected to GND. This leaves pins 7, 12 and 14. In this diagram it does not mention that pin 7 and 12 should be connected to GND. Also, Pin 14 is for VCC. Should this be connected to the calculators VCC? This same question holds true for the U19. Should Pin 7-13 be connected to GRN and Pin 14 connected to the calculators VCC? How about the U2 and U3. Should the Pin 8 on both chips be connected to GND and the Pin 16 on both chips be connected to the calculators VCC? In the document it only states that all unused "INPUTS" should be tied to GND. Also to test this Phase Counter, di I need to run all the output from U2 and U3, except CU4 and CT5, to GND?
Sorry for all the questions But I am also learning as I go.
Best Regards,

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