It looks like a PIC 18C252 running at 40MHz (100ns instruction cycle) should do the trick. It's available in a 28-pin SOIC package, which fits comfortably inside a single memory module. However, it needs an external clock to run at 40MHz, so an additional chip will be needed. Any suggestions?

The 18C252 has 32K of prom (OTP in the SOIC package), and it can do table reads from it.
That's enough memory for five, maybe six 4K modules (remember, HP41 ROM is 10 bits wide). This may be configured to be two 8K modules as if they were occupying adjacent ports, four 4K modules occupying all ports, or some combination; some ROMs can live below the 32K space, so one of them may fit in some of the free space there. And don't forget about bank-switching.

The idea is to bit-bang everything. Here is a rough outline of the code:

Power-up:
set the pin connected to the PWO line to be a wakeup pin.
probe the B3/B4 lines and remember where were are.
Wake-up:
(the first cycle after wake up is always at address 0,
so let's use that to synchronize).
while SYNC is LO, loop.
while SYNC is HI, loop.
(we are at Phi2 clock pulse 0)
Master-loop:
repeat 2 times
while Phi2 is HI, loop.
while Phi2 is LO, loop.
if PWO is LO, SLEEP.
repeat 14 times
while Phi2 is HI, loop.
while Phi2 is LO, loop.

(we are at Phi2 clock pulse 16)
repeat 16 times
while Phi1 is LO, loop.
read ISA line
shift into a RAM location
while Phi1 is LO, loop.
while Phi1 is HI, loop.
while Phi2 is LO, loop
(we are at Phi2 clock pulse 33)
while Phi2 is HI, loop
if address is in not in our range
while Phi2 is LO, loop
repeat 22 times
while Phi2 is HI, loop.
while Phi2 is LO, loop.
goto Master-loop.
(else)
prepare table base register for lower 8 bits
skip to next Phi2 pulse
read from table
skip to next Phi2 pulse
prepare table base register for upper 2 bits
skip to next Phi2 pulse
read from table
skip next 10 Phi2 pulses
(we are at rising edge of Phi2 pulse 46)
if SYNC is HI
repeat 8 times
output LSB of lower 8 bits
wait for Phi2 to go LO
shift one position right
wait for Phi2 to go HI
repeat 2 times
output LSB of upper 8 bits
wait for Phi2 to go LO
shift one position right
wait for Phi2 to go HI
else
skip next 10 Phi2 pulses
goto Master-Loop

I'm away at a conference all of next week; I hope to work on this during July. Any suggestions are, of course, welcome.

I'll start by using the EPROM version of the 18C252.

What you're describing (with PROM) is really only a replacement for a module or modules.

An MLDL is really defined (I guess) by the ability to both read from and write into the HP41 ROM space.

This si one reason for an earlier question about the number of write cycles the devices are rated for.

I would imagine that almost every user wil have requirements for a diferent set of modules, so unless the PROM version of the 18C252 is field programmable, and each user can program their own, I think that option may fall flat. Then there't the problem that the end user gets one chance...

That sort of brings us back to the Scenix chips, they are reprogrammable and can easily be reprogrammed from a PC. Only problem is their memory capacity is not very high (4-8Kb). Another option is to use an external RAM chip (for faster access) that is loaded from a bit serial EEPROM chip. This does increase the chip count to 3 chips, but they would probably still fit in a standard module.

You're right, I was describing a ROM module replacement. There is no real point in a true MLDL when we have tools such as V41 (the PC-based emulator) . All the debugging can be done on a PC, and then the final image can be transferred to the module (massaged into a set of constant definitions by a perl script or something).

For a real MLDL, we can add a couple of serial EEPROMs
(e.g., the 25256). EEPROMs take about a millisecond to write a byte; that's six machine cycles. I don't remember if the coconut cpu has any way of waiting for a peripheral event (does anyone have the listings for the card reader rom? that would probably help), but a trivial, if disgusting, way to busy-wait is to keep sending JMP +0 op codes next op-code while the eeprom is writing, and then give the real op-code!

OK, it's 5am in NYC, and I'd better get some sleep!

There is probably enough time between when the HP41 sends the address word until it needs the data word to use the serial EEPROM without an off chip RAM buffer. Although there are fast (1Mhz+) versions of the IIC bus that these chips use, they can be tricky to implement. Sometimes you have to retry the transaction. Also you may need active pullups on the bus, a simple resistor may not work. It should be OK with only an EEPROM chip or two hanging on it. Some of the PICs and mayby the Scenix chip have special hardware for doing the IIC bus directly.

I realize it wont fit in the case but what about 'Smartmedia' or memory sticks...