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OpenRPN and the 41CL - Printable Version +- HP Forums (https://archived.hpcalc.org/museumforum) +-- Forum: HP Museum Forums (https://archived.hpcalc.org/museumforum/forum-1.html) +--- Forum: Old HP Forum Archives (https://archived.hpcalc.org/museumforum/forum-2.html) +--- Thread: OpenRPN and the 41CL (/thread-198454.html) |
OpenRPN and the 41CL - snaggs - 09-29-2011 I posted a question a while ago about whether a calculator could be made like those from "the old days". Re: OpenRPN and the 41CL - Monte Dalrymple - 09-29-2011 The issue with putting the 41CL hardware into anything other Re: OpenRPN and the 41CL - Ángel Martin - 09-29-2011 Does "Anything other that a 41C body" include the "DIY5"? Rethorical question since I guess at this point only Eric has that information?
Re: OpenRPN and the 41CL - Monte Dalrymple - 09-29-2011 Yes. The display driver is not on the 41CL board, and any new 41CL and DIY4X/DIY5 - Eric Smith - 09-29-2011 Quote: The DIY4X already a high-performance 41-equivalent calculator. There would be no point to trying to put a 41CL board into a DIY4X or DIY5; it would take a huge amount of new engineering, and the result would be slower than the DIY5. Currently the DIY4X at 14 MHz is 6-14x faster than the original 41, depending on the specific functions used, and at 28 MHz is about 10-20x faster. Doubling the clock frequency doesn't double the performance because it introduces a wait state on the flash memory, and because some overhead such as display updating does not get faster. I haven't yet done any code optimization, and I think there will be at least 2x performance gain from that, and probably much more than that. The DIY5 hardware will be able to run at 48 MHz, with two wait states on the flash memory. I have some plans for reducing the performance degradation caused by the wait states. If someone wants to support engineering a *really* fast 41 replacement, I have a design for an FPGA datapath that runs more than 5000x faster than that of the 41. The idea is similar to Monte's NEWT processor in the 41CL, but is implemented as a 56-bit parallel data path rather than bit-serial. Some work is needed to finish the control portion. The actual speed would not be 5000x, just as the 41CL in Turbo50 mode isn't actually 50x faster than the original 41. It would also drain batteries much faster than the 41CL.
I designed that FPGA data path about ten years ago to satisfy my own curiosity as to how fast a Nut processor implemented in hardware could be. In an ASIC, it could easily be another factor of ten faster than the FPGA. I had no intention of using it in a product. However, once I have tooling for a DIY5 case, there is no reason why I couldn't at relatively low additional expense make a limited edition 41CMMMMM with the FPGA.
Re: OpenRPN and the 41CL - Hugh Evans - 09-29-2011 Please refrain from referencing OpenRPN in posts such as this. Especially since I'm considering a reboot of the project, and even maintain ownership of the domain, the name represents more than a concept. This form factor doesn't make sense: it measures 5"x9"x1.5" which is a lot more space than my 48gx takes up. The needs and desires I identified while managing the OpenRPN project are for pocket sized calculators of high build quality that are reliable, easy to use, maximize battery life, and nearly indestructible.
Before I formally announce a relaunch, I want to have at least one physical prototype (enclosure, clicky keys that work, and LCD) to show off. From there specs can be given for electronic hardware to be designed. $200 is the maximum price point I'm designing for. But one thing I specifically want to avoid this time is to start with a need for a platform. Hardware comes first, perhaps running ported code from WP34s, before any major public announcements are planned.
Re: 41CL and DIY4X/DIY5 - Howard Owen - 09-29-2011 Quote: The great thing about the 41CL is that it fits in a comfortable, familiar and well loved case. Your project is a brand new calculator, which has different design goals.
Quote: With that sort of tech, how about a massively parallel Nut consisting of hundreds of cores running multiple 41C images? Prime factorization might benefit from that. Only 0.5 kidding. :) edit: change radix to US standard.
Edited: 29 Sept 2011, 3:50 p.m.
Re: OpenRPN and the 41CL - Howard Owen - 09-29-2011 Quote:
A self-referential koan! OK, we need a euphemistic acronym then.
Re: 41CL and DIY4X/DIY5 - snaggs - 09-29-2011 I hadnt heard of this! Are they available?
Daniel.
Re: 41CL and DIY4X/DIY5 - Eric Smith - 09-29-2011 Quote:
Which doesn't contradict my point that it would make no sense to put a 41CL board into a DIY5 case.
Re: 41CL and DIY4X/DIY5 - Eric Smith - 09-29-2011 Are what available?
Certainly the DIY4X, DIY5, and the entirely hypothetical calculator with a parallel data path in an FPGA are not available. The DIY5 might be available in the future if we can figure out a way to produce it without losing money.
Re: OpenRPN and the 41CL - Egan Ford - 09-29-2011 That'd make a great 71B or 75C clone.
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