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Hi, just some pictures for my last project.



Great project, congratulation!

I see that the CPU is ok now. Let us know the next progress...


Edited: 1 May 2010, 5:25 a.m.

Are there any technical background information?

My main source is the patent # 4424563 for the description of the CPU. For the system I used the Assembler manual and other HP publications.

The global structure


I used fig. 1 of the patent to structure the fpga project :

  • schematics to structure the system
  • some verilog for ALU and Control Logic

For the global system I added a picoblaze controler
to 'hypervise' the system with the serial link of the board:

  • step CPU
  • trace until PC
  • ...

But now I think I have some timing problem with the Strataflash on the Nexys2 board. Sometimes the CPU can't 'read' the rom ...

Edited: 2 May 2010, 3:05 a.m.